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參數(shù)資料
| 型號： | IS65LV256AL-45UA3 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 LOW VOLTAGE CMOS STATIC RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 45 ns, PDSO28 |
| 封裝： | 0.330 MM, PLASTIC, SOP-28 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 113K |
| 代理商： | IS65LV256AL-45UA3 |
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
03/17/06
7
IS65LV256AL
IS62LV256AL
AC WAVEFORMS
WRITE CYCLE NO. 1 (
WE
Controlled)
(1,2)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCE
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CE
WE
D
OUT
D
IN
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-20 ns
Min.
-45 ns
Symbol
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Parameter
Max.
Min.
Max.
Unit
Write Cycle Time
20
—
45
—
ns
CE
to Write End
15
—
35
—
ns
Address Setup Time to Write End
14
—
25
—
ns
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
WE
Pulse Width
14
—
25
—
ns
Data Setup to Write End
13
—
20
—
ns
Data Hold from Write End
0
—
0
—
ns
WE
LOW to High-Z Output
—
8
—
20
ns
WE
HIGH to Low-Z Output
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with
OE
HIGH.
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| IS65LV256AL-45ULA3 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:32K x 8 LOW VOLTAGE CMOS STATIC RAM |
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| IS65WV102416BLL-25TA3 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1M x 16 HIGH-SPEED LOW POWER ASYNCHRONOUS CMOS STATIC RAM |
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