19 FN6659.3 November 22, 2011 If the application has a stable temperature environment that doesn’t change quickly, the 10 minute optio" />
參數(shù)資料
型號: ISL12022IBZ-T
廠商: Intersil
文件頁數(shù): 11/29頁
文件大?。?/td> 0K
描述: IC RTC/CALENDAR TEMP SNSR 8-SOIC
應(yīng)用說明: Addressing Power Issues in Real Time Clock Appls
產(chǎn)品培訓模塊: Solutions for Industrial Control Applications
標準包裝: 2,500
類型: 時鐘/日歷
特點: 警報器,夏令時,閏年,SRAM
存儲容量: 128B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
ISL12022
19
FN6659.3
November 22, 2011
If the application has a stable temperature environment that
doesn’t change quickly, the 10 minute option will work well and
the backup battery lifetime impact is minimized. If quick
temperature variations are expected (multiple cycles of more
than 10° within an hour), then the 1 minute option should be
considered and the slightly higher battery current figured into
overall battery life.
GAIN FACTOR OF AT BIT (BETA<4:0>)
Beta is specified to take care of the Cm variations of the crystal.
Most crystals specify Cm around 2.2fF. For example, if Cm > 2.2fF,
the actual AT steps may reduce from 1ppm/step to
approximately 0.80ppm/step. Beta is then used to adjust for this
variation and restore the step size to 1ppm/step.
BETA values are limited in the range from 01000 to 11111 as
shown in Table 16. To use Table 16, the device is tested at two AT
settings as shown in Equation 3:
where:
AT(max) = FOUT in ppm (at AT = 00H) and
AT(min) = FOUT in ppm (at AT = 3FH).
The BETA VALUES result is indexed in the right hand column and
the resulting Beta factor (for the register) is in the same row in
the left column.
The value for BETA should only be changed while the TSE
(Temperature Sense Enable) bit is “0”. The procedure for writing
the BETA register involves two steps. First, write the new value of
BETA with TSE = 0. Then write the same value of BETA with
TSE = 1. This will insure the next temperature sense cycle will use
the new BETA value.
Final Analog Trimming Register (FATR)
This register shows the final setting of AT after temperature
correction. It is read-only; the user cannot overwrite a value to this
register. This value is accessible as a means of monitoring the
temperature compensation function. See Table 17.
Final Digital Trimming Register (FDTR)
This Register shows the final setting of DT after temperature
correction. It is read-only; the user cannot overwrite a value to
this register. The value is accessible as a means of monitoring
the temperature compensation function. The corresponding
clock adjustment values are shown in Table 19. The DT setting
has both positive and negative settings to adjust for any offset in
the crystal.
.
TABLE 16. BETA VALUES
BETA<4:0>
AT STEP ADJUSTMENT
01000
0.5000
00111
0.5625
00110
0.6250
00101
0.6875
00100
0.7500
00011
0.8125
00010
0.8750
00001
0.9375
00000
1.0000
10000
1.0625
10001
1.1250
10010
1.1875
10011
1.2500
10100
1.3125
10101
1.3750
10110
1.4375
BETAVALUES
AT max
() AT min
()
()/63
=
(EQ. 3)
10111
1.5000
11000
1.5625
11001
1.6250
11010
1.6875
11011
1.7500
11100
1.8125
11101
1.8750
11110
1.9375
11111
2.0000
TABLE 17. FINAL ANALOG TRIMMING REGISTER
ADDR
7
6
54
32
1
0
0Eh
0
FATR5 FATR4 FATR3 FATR2 FATR1 FATR0
TABLE 18. FINAL DIGITAL TRIMMING REGISTER
ADDR
765
4
3
2
1
0
0Fh
0
FDTR4 FDTR3 FDTR2 FDTR1 FDTR0
TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL
TRIMMING REGISTER
FDTR<4:0>
DECIMAL
ppm ADJUSTMENT
00000
0
00001
1
30.5
00010
2
61
00011
3
91.5
00100
4
122
00101
5
152.5
00110
6
183
00111
7
213.5
01000
8
244
01001
9
274.5
TABLE 16. BETA VALUES (Continued)
BETA<4:0>
AT STEP ADJUSTMENT
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