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參數(shù)資料
| 型號(hào)： | ISL12022IBZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/29頁 |
| 文件大小： | 0K |
| 描述： | IC RTC/CALENDAR TEMP SNSR 8-SOIC |
| 應(yīng)用說明： | Addressing Power Issues in Real Time Clock Appls |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，夏令時(shí)，閏年，SRAM |
| 存儲(chǔ)容量： | 128B |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
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ISL12022
12
FN6659.3
November 22, 2011
Register Descriptions
The battery-backed registers are accessible following a slave
byte of “1101111x” and reads or writes to addresses [00h:2Fh].
The defined addresses and default values are described in the
Table 1. The battery backed general purpose SRAM has a
different slave address (1010111x), so it is not possible to
read/write that section of memory while accessing the registers.
REGISTER ACCESS
The contents of the registers can be modified by performing a
byte or a page write operation directly to any register address.
The registers are divided into 8 sections. They are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (9 bytes): Address 07h to 0Fh.
3. Alarm (6 bytes): Address 10h to 15h.
4. Time Stamp for Battery Status (5 bytes): Address 16h to 1Ah.
5. Time Stamp for VDD Status (5 bytes): Address 1Bh to 1Fh.
6. Daylight Savings Time (8 bytes): 20h to 27h.
7. TEMP (2 bytes): 28h to 29h
8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh
9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch
10. Crystal ALPHA at high temperature, ALPHA_H (1 byte): 2Dh
11. Scratch Pad (2 bytes): Address 2Eh and 2Fh
Write capability is allowable into the RTC registers (00h to 06h)
only when the WRTC bit (bit 6 of address 08h) is set to “1”. A
multi-byte read or write operation should be limited to one
section per operation for best RTC time keeping performance.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a sequential
read. For the RTC and Alarm registers, the read instruction
latches all clock registers into a buffer, so an update of the clock
does not change the time being read. At the end of a read, the
master supplies a stop condition to end the operation and free
the bus. After a read, the address remains at the previous
address +1 so the user can execute a current address read and
continue reading the next register. When the previous address is
2Fh, the next address will wrap around to 00h.
It is not necessary to set the WRTC bit prior to writing into the
control and status, alarm, and user SRAM registers.
TABLE 1. REGISTER MEMORY MAP
ADDR. SECTION
REG
NAME
BIT
RANGE DEFAULT
7
6
543
2
1
0
00h
RTC
SC
0
SC22
SC21
SC20
SC13
SC12
SC11
SC10
0 to 59
00h
01h
MN
0
MN22
MN21
MN20
MN13
MN12
MN11
MN10
0 to 59
00h
02h
HR
MIL
0
HR21
HR20
HR13
HR12
HR11
HR10
0 to 23
00h
03h
DT
0
DT21
DT20
DT13
DT12
DT11
DT10
1 to 31
01h
04h
MO
0
MO20
MO13
MO12
MO11
MO10
1 to 12
01h
05h
YR
YR23
YR22
YR21
YR20
YR13
YR12
YR11
YR10
0 to 99
00h
06h
DW
0
DW2
DW1
DW0
0 to 6
00h
07h
CSR
SR
BUSY
OSCF
DSTADJ
ALM
LVDD
LBAT85
LBAT75
RTCF
N/A
01h
08h
INT
ARST
WRTC
IM
FOBATB
FO3
FO2
FO1
FO0
N/A
01h
09h
PWR_VDD CLRTS
D
VDDTrip2
VDDTrip1
VDDTrip0
N/A
00h
0Ah
PWR_VBAT
RESEALB
VB85Tp2
VB85Tp1
VB85Tp0
VB75Tp2
VB75Tp1
VB75Tp0
N/A
00h
0Bh
ITRO
IDTR01
IDTR00
IATR05
IATR04
IATR03
IATR02
IATR01
IATR00
N/A
20h
0Ch
ALPHA
D
ALPHA6
ALPHA5
ALPHA4
ALPHA3
ALPHA2
ALPHA1
ALPHA0
N/A
46h
0Dh
BETA
TSE
BTSE
BTSR
BETA4
BETA3
BETA2
BETA1
BETA0
N/A
00h
0Eh
FATR
0
FFATR5
FATR4
FATR3
FATR2
FATR1
FATR0
N/A
00h
0Fh
FDTR
0
FDTR4
FDTR3
FDTR2
FDTR1
FDTR0
N/A
00h
10h
ALARM
SCA0
ESCA0
SCA022
SCA021
SCA020
SCA013
SCA012
SCA011
SCA010
00 to 59
00h
11h
MNA0
EMNA0 MNA022
MNA021
MNA020
MNA013
MNA012
MNA011
MNA010
00 to 59
00h
12h
HRA0
EHRA0
D
HRA021
HRA020
HRA013
HRA012
HRA011
HRA010
0 to 23
00h
13h
DTA0
EDTA0
D
DTA021
DTA020
DTA013
DTA012
DTA011
DTA010
01 to 31
00h
14h
MOA0
EMOA00
D
MOA020
MOA013
MOA012
MOA011
MOA010
01 to 12
00h
15h
DWA0
EDWA0
D
DWA02
DWA01
DWA00
0 to 6
00h
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| ISL12022IBZ-T7A | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK/CLNDR W/TEMP COMP 8 L RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12022M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation, and Auto Daylight Saving |
| ISL12022M_09 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation, and Auto Daylight Saving |
| ISL12022M_10 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving |
| ISL12022MA | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving |
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