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參數(shù)資料
| 型號： | ISL12022IBZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR TEMP SNSR 8-SOIC |
| 應用說明： | Addressing Power Issues in Real Time Clock Appls |
| 產(chǎn)品培訓模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 2,500 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，夏令時，閏年，SRAM |
| 存儲容量： | 128B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
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ISL12022
24
FN6659.3
November 22, 2011
User Registers (Accessed by
Using Slave Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of battery-backed user SRAM.
I2C Serial Interface
The ISL12022 supports a bi-directional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being controlled
is the slave. The master always initiates data transfers and provides
the clock for both transmit and receive operations. Therefore, the
ISL12022 operates as a slave device in all applications.
All communication over the I2C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 15). On power-
up of the ISL12022, the SDA pin is in the input mode.
All I2C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
ISL12022 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 15). A START condition is ignored
during the power-up sequence.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 15). A STOP condition at the end of a read
operation or at the end of a write operation to memory only
places the device in its standby mode.
An acknowledge (ACK) is a software convention used to indicate a
successful data transfer. The transmitting device, either master or
slave, releases the SDA bus after transmitting eight bits. During
the ninth clock cycle, the receiver pulls the SDA line LOW to
acknowledge the reception of the 8 bits of data (see Figure 16).
FIGURE 15. VALID DATA CHANGES, START AND STOP CONDITIONS
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 17. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL12022
A
C
K
10
0
11
A
C
K
WRITE
SIGNAL AT SDA
00 00
11 1
ADDRESS
BYTE
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISL12022IBZ-T7A | 功能描述:實時時鐘 REAL TIME CLK/CLNDR W/TEMP COMP 8 L RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12022M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation, and Auto Daylight Saving |
| ISL12022M_09 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation, and Auto Daylight Saving |
| ISL12022M_10 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving |
| ISL12022MA | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving |
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