21 FN7575.5 September 5, 2012 Final Analog Trimming Register (FATR) This register shows the final setting of AT after temperature co" />
參數(shù)資料
型號： ISL12022MAIBZ-T
廠商： Intersil
文件頁數(shù)： 14/31頁
文件大?。?/td> 0K
描述： IC RTC/CALENDAR TEMP SNSR 20SOIC
產(chǎn)品培訓(xùn)模塊： Solutions for Industrial Control Applications
標準包裝： 1,000
類型： 時鐘/日歷
特點： 警報器，夏令時，閏年，SRAM
存儲容量： 128B
時間格式： HH:MM:SS（12/24 小時）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
ISL12022MA
21
FN7575.5
September 5, 2012
Final Analog Trimming Register (FATR)
This register shows the final setting of AT after temperature
correction. It is read-only; the user cannot overwrite a value to this
register. This value is accessible as a means of monitoring the
temperature compensation function. See Table 18 and Table 19 (for
values).
Final Digital Trimming Register (FDTR)
This Register shows the final setting of DT after temperature
correction. It is read-only; the user cannot overwrite a value to
this register. The value is accessible as a means of monitoring
the temperature compensation function. The corresponding
clock adjustment values are shown in Table 20. The FDTR setting
has both positive and negative settings to adjust for any offset in
the crystal..
ALARM Registers (10h to 15h)
The alarm register bytes are set up identical to the RTC register
bytes, except that the MSB of each byte functions as an enable
bit (enable = “1”). These enable bits specify which alarm
registers (seconds, minutes, etc.) are used to make the
comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the alarm
registers and the RTC registers. As the RTC advances, the alarm
will be triggered once a match occurs between the alarm registers
and the RTC registers. Any one alarm register, multiple registers, or
all registers can be enabled for a match.
There are two alarm operation modes: Single Event and periodic
Interrupt Mode:
Single Event Mode is enabled by setting the Bit 7 on any of the
Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “0”, and
disabling the frequency output. This mode permits a one-time
match between the Alarm registers and the RTC registers.
Once this match occurs, the ALM bit is set to “1” and the
IRQ/FOUT output will be pulled low and will remain low until
the ALM bit is reset. This can be done manually or by using the
auto-reset feature.
Interrupt Mode is enabled by setting the Bit 7 on any of the
Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “1”, and
disabling the frequency output. The IRQ/FOUT output will now
be pulsed each time an alarm occurs. This means that once
the interrupt mode alarm is set, it will continue to alarm for
each occurring match of the alarm and present time. This
mode is convenient for hourly or daily hardware interrupts in
microcontroller applications such as security cameras or utility
meter reading.
10011
1.2500
10100
1.3125
10101
1.3750
10110
1.4375
10111
1.5000
11000
1.5625
11001
1.6250
11010
1.6875
11011
1.7500
11100
1.8125
11101
1.8750
11110
1.9375
11111
2.0000
TABLE 18. FINAL ANALOG TRIMMING REGISTER
ADDR
7
6
5432
10
0Eh
0
FATR5 FATR4 FATR3 FATR2 FATR1 FATR0
TABLE 19. FINAL DIGITAL TRIMMING REGISTER
ADDR
765
4
3
2
1
0
0Fh
0
FDTR4 FDTR3 FDTR2
FDTR1
FDTR0
TABLE 20. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL
TRIMMING REGISTER
FDTR<4:0>
DECIMAL
ppm ADJUSTMENT
00000
0
00001
1
30.5
00010
2
61
00011
3
91.5
00100
4
122
00101
5
152.5
TABLE 17. BETA VALUES (Continued)
BETA<4:0>
AT STEP ADJUSTMENT
00110
6
183
00111
7
213.5
01000
8
244
01001
9
274.5
01010
10
305
10000
0
10001
-1
-30.5
10010
-2
-61
10011
-3
-91.5
10100
-4
-122
10101
-5
-152.5
10110
-6
-183
10111
-7
-213.5
11000
-8
-244
11001
-9
-274.5
11010
-10
-305
TABLE 20. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL
TRIMMING REGISTER (Continued)
FDTR<4:0>
DECIMAL
ppm ADJUSTMENT
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