27 FN7575.5 September 5, 2012 Read Operation A Read operation consists of a three byte instruction, followed by one or more Data Byt" />
參數(shù)資料
型號(hào): ISL12022MAIBZ-T
廠商: Intersil
文件頁(yè)數(shù): 20/31頁(yè)
文件大?。?/td> 0K
描述: IC RTC/CALENDAR TEMP SNSR 20SOIC
產(chǎn)品培訓(xùn)模塊: Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝: 1,000
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,夏令時(shí),閏年,SRAM
存儲(chǔ)容量: 128B
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
ISL12022MA
27
FN7575.5
September 5, 2012
Read Operation
A Read operation consists of a three byte instruction, followed by
one or more Data Bytes (see Figure 20). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL12022MA responds
with an ACK. Then the ISL12022MA transmits Data Bytes as long
as the master responds with an ACK during the SCL cycle following
the eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of the
last Data Byte (see Figure 20).
The Data Bytes are from the memory location indicated by an
internal pointer. This pointer’s initial value is determined by the
Address Byte in the Read operation instruction, and increments
by one during transmission of each Data Byte. After reaching the
memory location 2Fh, the pointer “rolls over” to 00h, and the
device continues to output data for each ACK received.
Application Section
Power Supply Considerations
The ISL12022M contains programmed EEPROM registers which are
recalled to volatile RAM registers during initial power-up. These
registers contain DC voltage, frequency and temperature calibration
settings. Initial power-up can be either application of VBAT or VDD
power, whichever is first. It is important that the initial power-up
meet the power supply slew rate specification to avoid faulty
EEPROM power-up recall. Also, any glitches or low voltage DC
pauses should be avoided, as these may activate recall at a low
voltage and load erroneous data into the calibration registers. Note
that a very slow VDD ramp rate (outside data sheet limits) will
almost always trigger erroneous recall and should be avoided
entirely.
Battery Backup Details
The ISL12022MA has automatic switchover to battery backup
when the VDD drops below the VBAT mode threshold. A wide
variety of backup sources can be used, including standard and
rechargeable lithium, super-capacitors, or regulated secondary
sources. The serial interface is disabled in battery backup, while
the oscillator and RTC registers are operational. The SRAM
register contents are powered to preserve their contents as well.
The input voltage range for VBAT is 1.8V to 5.5V, but keep in mind
the temperature compensation only operates for VBAT >2.7V.
Note that the device is not guaranteed to operate with a VBAT <
1.8V, so the battery should be changed before discharging to that
level. It is strongly advised to monitor the low battery indicators in
the status registers and take action to replace discharged
batteries.
If a supercapacitor is used, it is possible that it may discharge to
below 1.8V during prolonged power-down. Once powered up, the
device may lose serial bus communications until both VDD and
VBAT are powered down together. To avoid that situation, including
situations where a battery may discharge deeply, the circuit in
Figure 21 can be used.
The diode, DBAT will add a small drop to the battery voltage but
will protect the circuit should battery voltage drop below 1.8V.
The jumper is added as a safeguard should the battery ever need
to be disconnected from the circuit.
The VDD negative slew rate should be limited to below the data
sheet spec (10V/ms) otherwise battery switchover can be
delayed, resulting in SRAM contents corruption and oscillator
operation interruption.
Some applications will require separate supplies for the RTC VDD
and the I2C pull-ups. This is not advised, as it may compromise
the operation of the I2C bus. For applications that do require
serial bus communication with the RTC VDD powered down, the
SDA pin must be pulled low during the time the RTC VDD ramps
down to 0V. Otherwise, the device may lose serial bus
communications once VDD is powered up, and will return to
normal operation ONLY once VDD and VBAT are both powered
down together.
Layout Considerations
The ISL12020M contains a quartz crystal and requires special
handling during PC board assembly. Excessive shock and vibrations
should be avoided. Ultrasound cleaning is not advisable. See Note 6
on page 6 in the electrical specifications table pertaining to solder
reflow effects on oscillator accuracy.
FIGURE 20. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT
SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
A
C
K
A
C
K
0
S
T
O
P
A
C
K
1
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
10
1
1111
10
1
11 11
FIGURE 21. SUGGESTED BATTERY BACKUP CIRCUIT
DBAT
CBAT
CIN
BAT43W
0.1F
VDD = 2.7V
VBAT = 1.8V
JBAT
ISL12022MA
VDD
GND
VBAT
TO 3.2V
TO 5.5V
+
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