- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9417 > ISL1219IUZ (Intersil)IC RTC LP BATT BACK SRAM 10MSOP PDF資料下載
參數(shù)資料
| 型號： | ISL1219IUZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC LP BATT BACK SRAM 10MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 98 |
| 類型： | 時間事件記錄器 |
| 特點： | 警報器，閏年，SRAM |
| 存儲容量： | 2B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1245 (CN2011-ZH PDF) |
15
FN6314.2
July 15, 2010
pin twice a second. Slower sampling significantly reduces
the supply current drain.
EVENT INPUT TIME BASE HYSTERESIS SELECTION
BITS (EHYS<1:0>)
These two bits select the time base hysteresis of the EVIN
pin to filter bouncing or noise of external event detection
circuits. The time filter can be set between 0 to 31.25 ms.
EVENT DETECT ENABLE BIT (EVEN)
This bit enables/disables the Event Detect function of the
ISL1219. When this bit is set to “1”, the Event Detect and
Time Stamp are active. When this bit is cleared to “0”, the
Event Detect and Time Stamp are disabled. Only the first
Event is Time Stamped in a series of Events between Event
resets (see EVT bit in the Status Register).
RTC HALT ON EVENT DETECT BIT (RTCHLT)
This bit sets the RTC registers to continue or halt counting
upon an Event Detect triggered by the EV pin. The time
keeping function will cease when RTCHLT is set to “1”, the
RTC will discontinue incrementing if an event is detected.
Counting will resume when there is a valid write to the RTC
registers (i.e. time set). The RTCHLT is cleared to “0” after
the write to the RTC registers.
Note: This function requires that the event detection is
enabled (see EVEN bit).
EVENT OUTPUT IN BATTERY MODE ENABLE BIT
(EVBATB)
This bit enables/disables the EVDET pin during battery
backup mode (i.e. VBAT pin supply ON). When the EVBATB
is set to “1”, the Event Detect Output is disabled in battery
backup mode. When the EVBATB is cleared to “0”, the Event
Detect output is enabled in battery backup mode.This
feature can be used to save power during battery mode.
EVENT CURRENT SOURCE ENABLE BIT (EVIENB)
This bit enables/disables the internal pull-up current source
used for the EVIN pin. When the EVIENB bit is set to “1”, the
pull-up current source is always disabled. When the EVIENB
bit is cleared to “0”, the pull-up current source is enabled
(current source is approximately 1A).
Analog Trimming Register
ANALOG TRIMMING REGISTER (ATR<5:0>)
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34 to
+80ppm to the nominal frequency compensation. The
combination of analog and digital trimming can give up to -94
to +140ppm of total adjustment.
The effective on-chip series load capacitance, CLOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). CLOAD is changed via two digitally
controlled capacitors, CX1 and CX2, connected from the X1
The effective series load capacitance is the combination of
CX1 and CX2:
For example, CLOAD(ATR = 00000) = 12.5pF,
CLOAD(ATR = 100000) = 4.5pF, and CLOAD(ATR = 011111)
= 20.25pF. The entire range for the series combination of
load capacitance goes from 4.5pF to 20.25pF in 0.25pF
steps. Note that these are typical values.
BATTERY MODE ATR SELECTION (BMATR <1:0>)
Since the accuracy of the crystal oscillator is dependent on
the VDD/VBAT operation, the ISL1219 provides the capability
to adjust the capacitance between VDD and VBAT when the
device switches between power sources.
TABLE 10.
ESMP1
ESMP0
EVENT SAMPLING RATE
0
Always ON
01
2Hz
10
1Hz
11
1/4Hz
TABLE 11.
EHYS1
EHYS0
TIME BASE HYSTERESIS
0
0 (pull-up always on)
0
1
3.9ms
1
0
15.625ms
1
31.25ms
FIGURE 13. DIAGRAM OF ATR
CX1
X1
X2
CRYSTAL
OSCILLATOR
CX2
CX
16 b5
8b4 4 b3 2b2 1 b1 0.5b0 9
+
+
+
+
+
+
()pF
=
(EQ. 1)
CLOAD
1
CX1
-----------
1
CX2
-----------
+
-----------------------------------
=
CLOAD
16 b5
8 b4 4 b3 2 b2 1 b1 0.5 b0 9
+
+
+
+
+
+
2
-----------------------------------------------------------------------------------------------------------------------------
pF
=
ISL1219
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-JW2-MZ | CONVERTER MOD DC/DC 15V 25W |
| ISL1209IU10Z | IC RTC LP BATT BACK SRAM 10MSOP |
| VE-JWV-MZ | CONVERTER MOD DC/DC 5.8V 25W |
| X9313WSZ | IC XDCP 32-TAP 10K 3-WIRE 8-SOIC |
| VE-JW3-MZ | CONVERTER MOD DC/DC 24V 25W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL1219IUZ-T | 功能描述:實時時鐘 REAL TIME CLKRTC IN RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL1220 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:I2C㈢ Real Time Clock/Calendar with Frequency Output |
| ISL1220IUZ | 功能描述:實時時鐘 REAL TIME CLKRTC IN RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL1220IUZ-T | 功能描述:實時時鐘 REAL TIME CLKRTC IN RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL1221 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。