參數資料
| 型號： | ISL267817IUZ-T |
| 廠商： | Intersil |
| 文件頁數： | 13/18頁 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE |
| 標準包裝： | 2,500 |
| 系列： | * |
ISL267817
4
FN7877.2
April 19, 2012
Absolute Maximum Ratings
Thermal Information
Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +VCC+0.3V
Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +VCC+0.3V
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . .-0.3V to +VCC+0.3V
Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
120
64
8 Ld MSOP Package (Notes 4, 5). . . . . . . . .
165
64
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For
θJC, the “case temp” location is taken at the package top center.
Electrical Specifications +VCC = +5V, fDCLOCK =3.2MHz, fS = 200kSPS, VREF = 2.5V; VCM = VREF, Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6)
UNITS
ANALOG INPUT (Note 7)
|AIN|
Full-Scale Input Span
+IN – (–IN)
-VREF
+VREF
V
Absolute Input Voltage
+IN
-0.3
+VCC +0.3
V
–IN
-0.3
+VCC +0.3
V
CVIN
Input Capacitance
Sample/Hold Mode
13/6
pF
ILEAK
Input DC Leakage Current
-1
0.01
1
A
SYSTEM PERFORMANCE
NResolution
12
Bits
No Missing Codes
12
Bits
INL
Integral Nonlinearity
-1
±0.5
1
LSB
DNL
Differential Nonlinearity
-1
±0.4
1
LSB
OFFSET
Zero-Code Error
-6
±0.25
6
LSB
GAIN
Gain Error
-4
±0.12
4
LSB
CMRR
Common-Mode Rejection
80
dB
PSRR
Power Supply Rejection
82
dB
SAMPLING DYNAMICS
tCONV
Conversion Time
fDCLOCK = 3.2MHz
12
Clk Cycles
tACQ
Acquisition Time
1.5
Clk Cycles
fmax
Throughput Rate
200
kSPS
DYNAMIC CHARACTERISTICS
THD
Total Harmonic Distortion
VIN = 5.0VP-P at fIN = 1kHz
-85
dB
VIN = 5.0VP-P at fIN = 5kHz
-84
dB
SINAD
Signal-to (Noise + Distortion) Ratio
VIN = 5.0VP-P at fIN = 1kHz
71
dB
SFDR
Spurious Free Dynamic Range
VIN = 5.0VP-P at fIN = 1kHz
85
dB
BW
Full Power Bandwidth
At –3dB
15
MHz
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