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| 型號(hào)： | ISL267817IUZ-T |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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ISL267817
11
FN7877.2
April 19, 2012
Functional Description
The ISL267817 is based on a successive approximation register
(SAR) architecture utilizing capacitive charge redistribution
digital to analog converters (DACs). Figure 25 shows a simplified
representation of the converter. During the acquisition phase
(ACQ), the differential input is stored on the sampling capacitors
(CS). The comparator is in a balanced state since the switch
across its inputs is closed. The signal is fully acquired after tACQ
has elapsed, and the switches then transition to the conversion
phase (CONV) so the stored voltage may be converted to digital
format. The comparator will become unbalanced when the
differential switch opens and the input switches transition
(assuming that the stored voltage is not exactly at mid-scale).
The comparator output reflects whether the stored voltage is
above or below mid-scale, which sets the value of the MSB. The
SAR logic then forces the capacitive DACs to adjust up or down by
one quarter of full-scale by switching in binarily weighted
capacitors. Again, the comparator output reflects whether the
stored voltage is above or below the new value, setting the value
of the next lowest bit. This process repeats until all 12 bits have
been resolved.
An external clock must be applied to the DCLOCK pin to generate
a conversion result. The allowable frequency range for DCLOCK is
10kHz to 3.2MHz (625SPS to 200kSPS). Serial output data is
transmitted on the falling edge of DCLOCK. The receiving device
(FPGA, DSP or Microcontroller) may latch the data on the rising
edge of DCLOCK to maximize set-up and hold times.
A stable, low-noise reference voltage must be applied to the VREF
pin to set the full-scale input range and common-mode voltage. See
“Voltage Reference Input” on page 12 for more details.
ADC Transfer Function
The output coding for the ISL267817 is twos complement. The
first code transition occurs at successive LSB values (i.e., 1 LSB,
2 LSB, and so on). The LSB size is 2*VREF/4096. The ideal
transfer characteristic of the ISL267817 is shown in Figure 26.
Analog Input
The ISL267817 features a fully differential input with a nominal
full-scale range equal to twice the applied VREF voltage. Each
input swings VREF VP-P, 180° out-of-phase from one another for
a total differential input of 2*VREF (refer to Figure 27).
FIGURE 24. REFERENCE CURRENT vs TEMPERATURE (CODE = FF8h)
Typical Performance Characteristics T
A = +25°C, VCC = 5V, VREF = 2.5V, fSAMPLE = 200kHz,
fCLK =16*fSAMPLE, unless otherwise specified. (Continued)
0
5
10
15
20
25
30
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
REFERE
N
C
E
CURRENT
(A)
FIGURE 25. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
+IN
–IN
VREF
ACQ
CONV
ACQ
CONV
DA
C
D
A
C
SAR
LOGIC
FIGURE 26. IDEAL TRANSFER CHARACTERISTICS
FIGURE 27. DIFFERENTIAL INPUT SIGNALING
1LSB = 2VREF/4096
100...000
100...001
100...010
111...111
000...000
000...001
011...110
011...111
AD
C
CO
DE
ANALOG INPUT
+IN
–(–IN)
–VREF
+ LSB
+VREF
– 1LSB
0V
+VREF
– 1LSB
ISL267817
VCM
VREF PP
+IN
–IN
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| ISL267817IUZ-T7A | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12 Bit 200kSPS SAR ADC 8LD RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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| ISL28005_10 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Micropower, Rail-to-Rail Input Current Sense Amplifier with Voltage Output |
| ISL28005_11 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Micropower, Rail-to-Rail Input Current Sense Amplifier |
| ISL28005FH-100EVAL1Z | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ISL28005FH EVALRD 1 5LD GAIN OF 100 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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