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參數(shù)資料
| 型號(hào)： | ISL45042AIRZ-TK |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 0K |
| 描述： | IC LCD CALIBRATOR 8-TDFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 校準(zhǔn)器 |
| 應(yīng)用： | LCD 顯示器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
4
FN6158.4
July 9, 2008
Application Information
The application circuit to adjust the VCOM voltage in an LCD
panel is shown in Figure 1. The ISL45042A has a 128-step
sink current resolution. The output is connected to an
external voltage divider, that results in decreasing the output
VCOM voltage as you increase the ISL45042A sink current.
CTL Pin
The adjustment of the output VCOM voltage and the
programming of the non-volatile memory are provided
through a single pin called CTL when the CE pin is high.
The output VCOM voltage is increased with a mid (VDD/2) to
high transition (0.8*VDD) on the CTL pin. The output VCOM
voltage is decreased with a mid (VDD/2) to low transition
or maximum value is reached on the 128 steps, the device
will not overflow or underflow beyond that minimum or
maximum value.
Programming of the non-volatile memory occurs when the
CTL pin exceeds 4.9V. The CTL signal needs to remain
above 4.9V for more than 200s. The level and timing
CTL EEPROM Programming
Signal Time
CTLPT
>4.9V
Full
200
-
s
Programming Time
PT
Full
-
100
ms
SET Voltage Resolution
SETVR
(Note 5)
Full
7
Bits
SET Differential Nonlinearity
SETDN
Monotonic Over-Temperature
Full
-
±1
LSB
SET Zero-Scale Error
SETZSE
Full
-
±2
LSB
SET Full-Scale Error
SETFSE
Full
-
±8
LSB
SET Current
ISET
Full
-
20
-
A
SET External Resistance
SETER
To GND, AVDD = 20V
Full
10
-
200
k
Ω
To GND, AVDD = 4.5V
Full
2.25
-
45
k
Ω
AVDD to SET Voltage Attenuation
AVDD to SET
Full
-
1:20
-
V/V
OUT Settling Time
OUTST
to ±0.5 LSB Error Band (Note 6)
Full
-
20
-
s
OUT Voltage Range
VOUT
Full
VSET + 0.5V
-
13
V
OUT Voltage Drift
OUTVD
(Note 6)
25 to 55
-
<10
-
mV
NOTES:
3. CTL signal only needs to be greater than 4.9V to program EEPROM.
4. Tested at AVDD = 20V.
5. The Counter value is set to mid-scale ±4 LSB’s in the Production.
6. Simulated and Determined via Design and NOT Directly Tested.
7. Simulated Maximum Current Draw when Programming EEPROM is 23mA; should be considered when designing Power Supply.
8. A Typical Current of 20A is Calculated using the AVDD = 10V and RSET = 24.9kΩ. Reference “RSET Resistor” on page 6.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9kΩ; Unless Otherwise Specified.
Typicals are at TA = +25°C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9) UNITS
RSET
FIGURE 1. VCOM ADJUSTMENT IN AN LCD PANEL
ISL45042A
SET
OUT
AVDD
R1
R2
AVDD
ISINK
VCOM
SINGLE PIXEL
CTL
CE
IN LCD PANEL
RED
GR
EE
N
BL
UE
+
-
COLUMN
DRIVER
ISL45042A
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