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參數(shù)資料
| 型號： | ISL45042AIRZ-TK |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LCD CALIBRATOR 8-TDFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 校準(zhǔn)器 |
| 應(yīng)用： | LCD 顯示器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
6
FN6158.4
July 9, 2008
values of: RSET = 24.9kΩ, R1 = 200kΩ, R2 = 243kΩ, and
AVDD = 10V.
RSET Resistor
The external RSET resistor sets the full-scale sink current that
determines the lowest voltage of the external voltage divider R1
1.75V. This will keep the output MOS transistor in the saturation
region. Expected current settings and 7-bit accuracy occurs
region. Figure 5 shows the internal connection for the output
MOS transistor. The value of the AVDD supply sets the voltage
at the source of the output transistor. This voltage is equal to
(Setting/128) x (AVDD/20). The ISET current is therefore equal
to (Setting/128) x (AVDD/20 x RSET). The value of the Drain
Equation 2, should be determined (setting equal to 128) so the
minimum value of VOUT is greater than 1.75V + AVDD/20.
Power Supply Sequence
The recommendation for power supply sequence would be
to power down the part first (VDD, AVDD), after 100ms if
programming has occurred, and then power-down the
control power supplies (CTL, CE).
Verifying the Programmed Value
The following sequence can be used to verify the
programmed value without having to sequence the VDD
supply. To verify the programmed value, follow the following
steps. The ISL45042A will read memory contents and be set
to that value when the CE pin is grounded.
1. Power-up the ISL45042A.
2. CE pin = VDD.
3. Change counter value with CTL pin to desired value.
4. CTL = more than 4.9V and 200ms. Counter value
programmed.
5. Change the counter value with CTL pin to a different
value.
6. CE pin = Ground.
7. Check that the output value is the one programmed in
Step 4.
Generating VDD and CE supply from a Larger
Voltage Source
The CE pin has an internal pull-down resistor (see
400k
Ω to 500kΩ. If your design is using a resistor divider
network to generate the 3.3V supply (for both VDD and CE to
enable programming) from a larger voltage source, the
400k
Ω (worst case) resistor needs to be taken into account
as a parallel resistance when the CE pin is connected to this
source. Another design concern is to be able to provide
enough supply current during programming. The ISL45042A
draws about 2mA during this process. Recommended
resistor values are shown in Figure 6. This design will result
in an additional 0.83mA quiescent current flowing through
resistors RA and RB.
TABLE 1. CALCULATED VCOM OUTPUT VOLTAGES
SETTING VALUE
VOUT
1
5.468
10
5.313
20
5.141
30
4.969
40
4.797
50
4.625
60
4.453
70
4.281
80
4.109
90
3.936
100
3.764
110
3.592
128
3.282
FIGURE 5. OUTPUT CONNECTION CIRCUIT EXAMPLE
AVDD = 15V
RSET
VOUT PIN
R1
R2
AVDD
VSAT
0.5V
ISET PIN
SETTING
128
---------------------------- x
AV
DD
20
------------------
FIGURE 6. APPLICATION GENERATING VDD AND VCE
VOLTAGES
VCC = 5V
SCHMITT
TRIGGER
CE LOGIC
RINTERNAL = 400kΩ to 500kΩ
RA
RB
2k
Ω
4k
Ω
ISL45042A
CE
VCE
ISL45042A
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