參數(shù)資料
型號: ISL51002-EVALZ
廠商: Intersil
文件頁數(shù): 10/33頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR ISL51002
標準包裝: 1
系列: *
18
FN6164.3
February 29, 2012
0x2D
XTAL CLOCK FREQ,
(0x19)
4:0
Crystal Clock Frequency
Crystal clock frequency in MHz (decimal).
0x00: Test Mode, Do not use.
0x01 through 0x0A: 10MHz, APLL DIV = 35 (0x23)
0x0B: 11MHz, APLL DIV = 32
0x0C: 12MHz, APLL DIV = 30
0x0D: 13MHz, APLL DIV = 27
0x0E: 14MHz, APLL DIV = 25
0x0F: 15MHz, APLL DIV = 24
0x10: 16MHz, APLL DIV = 22
0x11: 17MHz, APLL DIV = 21
0x12: 18MHz, APLL DIV = 20
0x13: 19MHz, APLL DIV = 19
0x14: 20MHz, APLL DIV = 18
0x15: 21MHz, APLL DIV = 17
0x16: 22MHz, APLL DIV = 16
0x17: 23MHz, APLL DIV = 16
0x18: 24MHz, APLL DIV = 15
0x19: 25MHz, APLL DIV = 14
0x1A: 26MHz, APLL DIV = 14
0x1B: 27MHz, APLL DIV = 13
0x1C: 28MHz, APLL DIV = 13
0x1D: 29MHz, APLL DIV = 13
0x1E: 30MHz, APLL DIV = 12
0x1F: 31MHz, APLL DIV = 12
0x2E
AFE Bandwidth, (0x0E)
3:0
AFE BW
-3dB point for AFE lowpass filter
0: 9MHz
1: 10MHz
2: 11MHz
3: 12MHz
4: 14MHz
5: 17MHz
6: 21 MHz
7: 24MHz
8: 30MHz
9: 38MHz
A: 50MHz
B: 75MHz
C: 83MHz
D: 105MHz
E: 149MHz (default)
F: 450MHz
0x2F
HSYNC Slicer Thresholds,
(0x44)
All values referred to
voltage at HSYNC input pin,
300mV hysteresis
3:0
Selected HSYNC Threshold HSYNC slicer threshold for selected input channel (only 3-bits
used, lowest bit is ignored):
0000 = lowest (0.4V)
0100 = default (1.15V)
1111 = highest (3.2V)
7:4
Unselected HSYNC
Threshold
HSYNC threshold for monitoring unselected inputs. See
Selected HSYNC Threshold for values.
0x30
SOG Slicer Thresholds,
(0x66)
3:0
SOG Threshold
SOG slicer threshold:
0000 = lowest (0mV)
0110 = default (120mV)
1111 = highest (300mV)
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
BITS
FUNCTION NAME
DESCRIPTION
ISL51002
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