參數(shù)資料
型號(hào)： ISL51002-EVALZ
廠商： Intersil
文件頁數(shù)： 13/33頁
文件大小： 0K
描述： EVAL BOARD FOR ISL51002
標(biāo)準(zhǔn)包裝： 1
系列： *
20
FN6164.3
February 29, 2012
0x44
VSYNC Period MSB,
(read only)
3:0
VSYNC Period MSB
These bits report a 12-bit value containing the width of one frame
(= 2 fields for interlaced, = 1 field for progressive) of video.
VSYNC period for measured channel =
256*VSYNC Period MSB + VSYNC Period LSB
Units are either number of HSYNC periods or number of
fCRYSTAL/512 periods, depending on setting of VSYNC Units
register.
0x45
VSYNC Period LSB,
(read only)
7:0
VSYNC Period LSB
0x46
VSYNC Width,
(read only)
6:0
VSYNC Width
This register reports a 7-bit value containing the width the
VSYNC pulse. The value returned is for true VSYNC only: it
does not include serrations, EQ pulses, Macrovision pulses,
etc. Units are either number of HSYNC periods or number of
fCRYSTAL/512 periods, depending on setting of VSYNC Units
register.
0x47
DE Start MSB, (0x00)
1:0
DE Start MSB
10-bit value containing the number of pixel clocks between the
trailing edge of HSOUT and the first valid pixel. SXGA default
values.
0x48
DE Start LSB, (0xF6)
7:0
DE Start LSB
0x49
DE Width MSB, (0x05)
3:0
DE Width MSB
12-bit value containing the number of visible image pixels.
SXGA default values.
0x4A
DE Width LSB, (0x00)
7:0
DE Width LSB
0x4B
Line Start MSB, (0x00)
1:0
Line Start MSB
10-bit value containing the number of lines between the trailing
edge of VSYNCOUT and the first valid line. SXGA default
values.
0x4C
Line Start LSB, (0x26)
7:0
Line Start LSB
0x4D
Line Width MSB, (0x04)
3:0
Line Width MSB
12-bit value containing the number of visible lines.
SXGA default values.
0x4E
Line Width LSB, (0x00)
7:0
Line Width LSB
0x4F
Measurement Configuration,
(0x00)
0
VSYNC Units
0: VSYNC measurement reported in units of lines
(HSYNC periods)
1: VSYNC measurement reported in units of 512 crystal clock
periods
1
VSYNC_Linecount_Mode
0: New method (Integer count of HSOUTs)
1: Old method (Time measurement with rounding errors)
AUTO ADJUST REGISTERS
0x50
Phase ADJ CMD FN, (0x00)
2:0
PADJ Function
Note: A write to this register executes the command contained
in the three LSBs of the word written. Commands:
000: Reserved
001: Reserved
010: Reserved
011: SetPhase
100: Set DE
101: Reserved
110: Reserved
111: Reserved
0x51
Phase ADJ STATUS,
(read only)
7
PADJ Busy
0: Phase Adjustment function idle
1: Phase Adjustment in progress
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
BITS
FUNCTION NAME
DESCRIPTION
ISL51002
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