Voltage on VD (re" />
參數(shù)資料
型號： ISL54100AHDMI-EVALZ
廠商： Intersil
文件頁數(shù)： 15/21頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR ISL54100AHDMI
標準包裝： 1
系列： *
3
FN6725.0
June 17, 2008
Absolute Maximum Ratings
Thermal Information
Voltage on VD (referenced to GND). . . . . . . . . . . . . . . . . . . . . . 4.0V
Voltage on any Input Pin (referenced to GND) . . . -0.3V to VD+0.3V
Voltage on any “5V Tolerant” Input Pin
(referenced to GND). . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Current into any Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
ESD Classification
Human Body Model . . . >4000V, higher voltage testing in progress
Machine Model . . . . . . . . >200V, higher voltage testing in progress
Thermal Resistance (Typical, Note 1)
θ
JA (°C/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD = 3.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1.
θ
JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Specifications apply for VD = 3.3V, pixel rate = 165MHz, TA = +25°C, RES_TERM = 1kΩ, RES_BIAS = 3.16kΩ,
TMDS output load = 50
Ω, TMDS output termination voltage V
TERM = 3.0V unless otherwise noted.
SYMBOL
PARAMETER
COMMENT
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
FULL CHANNEL CHARACTERISTICS
fDATA_MAX
Maximum Rx Clock Frequency/Pixel Rate
(Note 3)
165
225
MHz
fDATA_MIN
Minimum Rx Clock Frequency/Pixel Rate
25
MHz
TMDS RECEIVER CHARACTERISTICS
VSENS
Minimum Differential Input Sensitivity
50
150
mVP-P
R50
50
Ω Termination Resistance
45
50
55
Ω
R100
100
Ω Termination Resistance
90
97
110
Ω
CLKDUTY
Rx Clock Duty Cycle
20
80
%
TMDS TRANSMITTER CHARACTERISTICS
jTX_CLOCK
Total Jitter on Clock Outputs
Independent of incoming jitter
32
ps
jTX_DATA
Total Jitter on Data Outputs
Independent of incoming jitter
52
ps
SKEWINTRA Intra-Pair (+ to -) Differential Skew
±4
ps
SKEWINTER Inter-Pair (channel-to-channel) Skew
Added with respect to incoming
inter-pair skew
2UI
tRISE
Rise Time into 50
Ω Load to 3.3V
20% to 80%
80
240
ps
tFALL
Fall Time into 50
Ω Load to 3.3V
20% to 80%
80
240
ps
TX VOH
Single-Ended High Level Output Voltage
VTERM - 10
VTERM + 10
mV
TX VOL
Single-Ended Low Level Output Voltage
VTERM - 600
VTERM - 400
mV
DIGITAL SCHMITT INPUT CHARACTERISTICS
VIH
High Threshold Voltage
2.0
V
VIL
High to Low Threshold Voltage
0.8
V
I
Input Leakage Current
±10
nA
RPU
Internal Pull-Up Resistance
SDA and SCL pins
65
k
Ω
RPD
Internal Pull-Down Resistance
AUTO_CH_SEL, CH_SEL_x,
RESET, ADDRx, PD pins
60
k
Ω
CIN
Input Capacitance
5pF
ISL54100A, ISL54101A, ISL54102A
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