FN7510.0 February 14, 2008 120 VLUMAx2IN
參數(shù)資料
型號(hào): ISL59450IQZ
廠(chǎng)商: Intersil
文件頁(yè)數(shù): 6/37頁(yè)
文件大小: 0K
描述: IC SWITCH VID CRSSPNT 128-MQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
14
FN7510.0
February 14, 2008
120
VLUMAx2INA
Analog Input. Luma Reference Level for DC-Restore when AV = 2, for Channel A. When using the YPbPr
inputs in RGB mode, this DC voltage sets the clamp voltage of the Pr/R and Pb/B signals for Channel A
when the gain is set to x2. When using the YPbPr inputs in YPbPr mode, this DC voltage sets the clamp
voltage of the Pr/R and Pb/B signals for Channel A.This input is typically tied together with VLUMAx2INB
and driven with the same voltage. The Y/G signal is clamped to the VTIPINA voltage in master mode and
VLUMAx2INA in slave mode.
119
VLUMAx1INA
Analog Input. Luma Reference Level for DC-Restore when AV = 1, for Channel A. When using the YPbPr
inputs in RGB mode, this DC voltage sets the clamp voltage of the R and B signals for Channel A when
the gain is set to x1. This input is typically tied together with VLUMAx1INB and driven with the same voltage.
The Y/G signal is clamped to the VTIPINA voltage in master mode and VLUMAx1INA in slave mode.
118
VSLICEINA
Analog Input. Slicer comparator threshold for extracting composite sync from video, for Channel A. This DC
voltage is typically set to 0.07V above VTIPINA, creating a sync tip slicing level of 70mV. This input is
typically tied together with VSLICEINB and driven with the same voltage.
117
VTIPINA
Analog Input. Sync Tip Reference Level for DC-Restore, for Channel A. This DC voltage sets the level of
the sync tip of Channel A’s output signal. This input is typically tied together with VTIPINB and driven with
the same voltage. In RGB mode (with no Sync-on-Green), this sets the black level of the G channel.
45
VCHROMAx2INB
Analog Input. Chroma Reference Level for DC-Restore when AV = 2, for Channel A. This DC voltage sets
the midpoint voltage of the C signal (S-Video) and the Pb, Pr signals (Component video) for Channel A when
the gain is set to x2. When using the YPbPr inputs in YPbPr mode, this DC voltage sets the clamp voltage
of the Pr/R and Pb/B signals for Channel B. This input is typically tied together with VCHROMAx2INA and
driven with the same voltage.
46
VCHROMAx1INB
Analog Input. Chroma Reference Level for DC-Restore when AV = 1, for Channel A. This voltage sets the
midpoint voltage of the C signal (S-Video) and the Pb, Pr signals (Component video) for Channel A when
the gain is set to x1. When using the YPbPr inputs in YPbPr mode, this DC voltage sets the clamp voltage
of the Pr/R and Pb/B signals for Channel B. This input is typically tied together with VCHROMAx1INA and
driven with the same voltage.
47
VLUMAx2INB
Analog Input. Luma Reference Level for DC-Restore when AV = 2, for Channel B. When using the YPbPr
inputs in RGB mode, this DC voltage sets the clamp voltage of the R and B signals for Channel B when
the gain is set to x2. This input is typically tied together with VLUMAx2INA and driven with the same voltage.
The Y/G signal is clamped to the VTIPINB voltage in master mode and VLUMAx2INB in slave mode.
48
VLUMAx1INB
Analog Input. Luma Reference Level for DC-Restore when AV = 1, for Channel B. When using the YPbPr
inputs in RGB mode, this DC voltage sets the clamp voltage of the R and B signals for Channel B when
the gain is set to x1. This input is typically tied together with VLUMAx1INA and driven with the same voltage.
The Y/G signal is clamped to the VTIPINB voltage in master mode and VLUMAx1INB in slave mode.
49
VSLICEINB
Analog Input. Slicer comparator threshold for extracting composite sync from video, for Channel B. This DC
voltage is typically set to 0.07V above VTIPINB, creating a sync tip slicing level of 70mV. This input is
typically tied together with VSLICEINA and driven with the same voltage.
50
VTIPINB
Analog Input. Sync Tip Reference Level for DC-Restore, for Channel B. This DC voltage sets the level of
the sync tip of Channel B’s output signal. This input is typically tied together with VTIPINA and driven with
the same voltage. In RGB mode (with no Sync-on-Green), this sets the black level of the G channel.
I2C CONTROL AND I/O
85
SDA
I2C Bus Data I/O
82
SCL
I2C Bus Clock
92
Address
Digital Input with internal pull-down. Sets I2C address: 0x84 if tied low, 0x8C if tied high. (300k pull-down)
IC RESET, ENABLE AND MISC.
77
Reset
5V Digital Input, with 3.5V logic threshold and a 300k pull-down. Tie to +5V for normal operation. Taking
Reset to 0V and back to 5V initializes all data registers to 0x00.
90
PowerDown
Digital Input with 300k pull-down. When this pin is taken high, all analog circuitry is disabled to minimize
power consumption. In PowerDown mode, the outputs are tri-stated while the I2C interface remains active
and all register data is retained.
POWER SUPPLIES
18, 20, 42, 125 VA
+5V Analog supply
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
ISL59450
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