參數(shù)資料
型號： ISL6315
廠商： Intersil Corporation
英文描述： Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers(帶集成MOSFET驅動器的雙相降壓PWM控制器)
中文描述： 兩相多相降壓PWM控制器，具有集成MOSFET驅動器（帶集成MOSFET的驅動器的雙相降壓的PWM控制器）
文件頁數(shù)： 14/20頁
文件大?。?/td> 394K
代理商： ISL6315
14
FN9222.1
July 18, 2007
and E represents the total output capacitance and its
equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6315) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
0
; typically 0.1 to 0.3 of F
SW
) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F
0dB
and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 8. Use the following guidelines for locating the
poles and zeros of the compensation network:
1. Select a value for R1 (1k
Ω
to 5k
Ω
, typically). Calculate
value for R2 for desired converter bandwidth (F
0
).
2. Calculate C1 such that F
Z1
is placed at a fraction of the F
LC
,
at 0.1 to 0.75 of F
LC
(to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
CE
/F
LC
, the lower the F
Z1
frequency (to maximize phase boost).
3. Calculate C2 such that F
P1
is placed at F
CE
.
4. Calculate R3 such that F
Z2
is placed at F
LC
. Calculate C3
such that F
P2
is placed below F
SW
(typically, 0.5 to 1.0
times F
SW
). F
SW
represents the per-channel switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
P2
lower in
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
MOD
), feedback
compensation (G
FB
) and closed-loop response (G
CL
):
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 9 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
P2
against the capabilities of the error
amplifier. The closed loop gain, G
CL
, is constructed on the
log-log graph of Figure 9 by adding the modulator gain, G
MOD
(in dB), to the feedback compensation gain, G
FB
(in dB). This
is equivalent to multiplying the modulator transfer function and
the compensation transfer function and then plotting the
resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
F
LC
2
π
L C
---------------------------
=
F
CE
-----------------------
=
(EQ. 8)
R2
V
R1 F
MAX
IN
LC
---------------------------------------------
=
(EQ. 9)
C1
LC
-----------------------------------------------
=
(EQ. 10)
C2
CE
1
–
---------------------------------------------------------
=
(EQ. 11)
R3
LC
------------
1
–
---------------------
=
C3
SW
-------------------------------------------------
=
(EQ. 12)
G
MOD
f
( )
d
V
OSC
-----------------------------
1
s f
( )
E
D
+
(
)
C
s
2
f
( )
L C
+
+
-----------------------------+
=
G
FB
f
( )
C1
C2
(
)
--------+
=
)
C3
1
s f
( )
R3 C3
+
(
)
1
s f
( )
R2
+
C2
----------------------
+
----------------------------------+
G
CL
f
( )
G
MOD
f
( )
G
FB
f
( )
=
where s f
( )
2
π
=
(EQ. 13)
F
Z1
-------------------------------
=
F
Z2
R3
)
C3
----------------------+
=
F
P1
2
π
R2
C2
--------+
----------------------------------------------
=
F
P2
-------------------------------
=
(EQ. 14)
0
F
P1
F
Z2
OPEN LOOP E/A GAIN
F
Z1
F
P2
F
LC
F
CE
COMPENSATION GAIN
CLOSED LOOP GAIN
G
FREQUENCY
MODULATOR GAIN
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
20
d
OSC
V
IN
----V
log
20
R1
log
LOG
L
F
0
G
MOD
G
FB
G
CL
ISL6315
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