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參數資料
| 型號： | ISL6315 |
| 廠商： | Intersil Corporation |
| 英文描述： | Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers(帶集成MOSFET驅動器的雙相降壓PWM控制器) |
| 中文描述： | 兩相多相降壓PWM控制器，具有集成MOSFET驅動器（帶集成MOSFET的驅動器的雙相降壓的PWM控制器） |
| 文件頁數： | 16/20頁 |
| 文件大?。?/td> | 394K |
| 代理商： | ISL6315 |
16
FN9222.1
July 18, 2007
different MOSFETs and different switching frequencies until
converging upon the best solution.
OUTPUT FILTER DESIGN
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the square
wave voltage at the phase nodes. Additionally, the output
capacitors must also provide the energy required by a fast
transient load during the short interval of time required by the
controller and power train to respond. Because it has a low
bandwidth compared to the switching frequency, the output
filter limits the system transient response leaving the output
capacitor bank to supply the load current or sink the inductor
currents, all while the current in the output inductors
increases or decreases to meet the load demand.
In high-speed converters, the output capacitor bank is
amongst the costlier (and often the physically largest) parts
of the circuit. Output filter design begins with consideration
of the critical load parameters: maximum size of the load
step,
Δ
I, the load-current slew rate, di/dt, and the maximum
allowable output voltage deviation under transient loading,
Δ
V
MAX
. Capacitors are characterized according to their
capacitance, ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates according to
the following equation:
The filter capacitor must have sufficiently low ESL and ESR
so that
Δ
V <
Δ
V
MAX
.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors is also responsible for the
majority of the output-voltage ripple. As the bulk capacitors
sink and source the inductor AC ripple current, a voltage
develops across the bulk-capacitor ESR equal to I
P-P
. Thus,
once the output capacitors are selected and a maximum
allowable ripple voltage, V
P-P(MAX)
, is determined from an
analysis of the available output voltage budget, the following
equation can be used to determine a lower limit on the
output inductance.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
Δ
V
MAX
. This places an upper limit on inductance.
4 C V
)
While the previous equation addresses the leading edge, the
following equation gives the upper limit on L for cases where
the trailing edge of the current transient causes a greater
output voltage deviation than the leading edge.
Normally, the trailing edge dictates the selection of L, since
duty cycles are usually less than 50%. Nevertheless, both
inequalities should be evaluated, and L should be selected
based on the lower of the two results. In all equations in this
paragraph, L is the per-channel inductance and C is the total
output bulk capacitance.
LAYOUT CONSIDERATIONS
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET was carrying channel current. During the
turnoff, current stops flowing in the upper MOSFET and is
picked up by the lower MOSFET. Any inductance in the
switched current path generates a large voltage spike during
the switching interval. Careful component selection, tight
layout of the critical components, and short, wide circuit
traces minimize the magnitude of voltage spikes.
There are two sets of critical components in a DC/DC
converter using a ISL6315 controller. The power
components are the most critical because they switch large
amounts of energy. Next are small signal components that
connect to sensitive nodes or supply critical bypassing
current and signal coupling.
Note that as the ISL6315 does not allow external adjustment
of the channel-to-channel current balancing (current
information is multiplexed across a single R
ISEN
resistor), it
Δ
V
ESL
(
)
di
dt
----
ESR
(
)Δ
I
+
≈
(EQ. 21)
L
ESR
V
f
S
V
IN
V
P-P MAX
------------–
)
V
OUT
)
≥
(EQ. 22)
L
Δ
I
(
--------------------------------
Δ
V
MAX
Δ
I ESR
–
(
)
≤
(EQ. 23)
L
----------------
)
2
Δ
I
(
Δ
V
MAX
Δ
I ESR
–
(
)
V
IN
V
O
–
(
)
≤
(EQ. 24)
ISL6315
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| ISL6315CRZ | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數:1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6315CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數:1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6315CRZ-TK | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數:1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6315IRZ | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數:1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
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