- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383156 > ISL6556ACR (INTERSIL CORP) Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application PDF資料下載
參數(shù)資料
| 型號： | ISL6556ACR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application |
| 中文描述： | SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, MO-220VHHD-2, QFN-32 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 702K |
| 代理商： | ISL6556ACR |
20
Once selected, the compensation values in Equations 21
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R
C
. Slowly increase the
value of R
C
while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C
C
will not need adjustment. Keep the value of C
C
from
Equations 21 unless some performance issue is noted.
The optional capacitor C
2
, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 12). Keep
a position available for C
2
, and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step,
I; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading,
V
MAX
. Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
The filter capacitor must have sufficiently low ESL and ESR
so that
V <
V
MAX
.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see
Interleaving
and
Equation 2), a voltage develops across the bulk-capacitor
ESR equal to I
C,PP
(ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
V
PP(MAX)
, determines the lower limit on the inductance.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
V
MAX
. This places an upper limit on inductance.
Equation 24 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 25
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
Input Supply Voltage Selection
The VCC input of the ISL6556A can be connected either
directly to a +5V supply or through a current limiting resistor to
a +12V supply. An integrated 5.8V shunt regulator maintains
the voltage on the VCC pin when a +12V supply is used. A
300
resistor is suggested for limiting the current into the
VCC pin to a worst-case maximum of approximately 25mA.
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in
MOSFETs
, and they establish the upper limit for
the switching frequency. The lower limit is established by the
requirement for fast transient response and small output-
voltage ripple as outlined in
Output Filter Design
. Choose the
lowest switching frequency that allows the regulator to meet
the transient-response requirements.
V
ESL
(
)
di
dt
----
ESR
(
)
I
+
≈
(EQ. 22)
L
ESR
(
)
V
-
NV
S
V
IN
V
PP MAX
(
-------f
)
V
OUT
)
≥
(EQ. 23)
L
O
I
(
)
2
2NCV
V
MAX
-
I ESR
)
[
]
≤
(EQ. 24)
L
(
-1.25
V
MAX
-
I ESR
)
NC
)
2
I
)
[
]
V
IN
-
V
O
(
)
≤
(EQ. 25)
ISL6556A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL6556ACR-T | Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application |
| ISL6556ACRZ | Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application |
| ISL6556ACRZ-T | PWM Controller with Wide Input Range 8-PDIP -40 to 85 |
| ISL6556ACB-T | Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application |
| ISL6556ACBZ-T | Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6556ACR-T | 功能描述:IC CTRLR MULTIPHASE VRM10 32-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,000 系列:- 應(yīng)用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應(yīng)商設(shè)備封裝:42-WLP 包裝:帶卷 (TR) |
| ISL6556ACRZ | 功能描述:IC CTRLR MULTIPHASE VRM10 32-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標(biāo)準(zhǔn)包裝:43 系列:- 應(yīng)用:控制器，Intel VR11 輸入電壓:5 V ~ 12 V 輸出數(shù):1 輸出電壓:0.5 V ~ 1.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-QFN（7x7） 包裝:管件 |
| ISL6556ACRZ-T | 功能描述:IC CTRLR MULTIPHASE VRM10 32-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標(biāo)準(zhǔn)包裝:43 系列:- 應(yīng)用:控制器，Intel VR11 輸入電壓:5 V ~ 12 V 輸出數(shù):1 輸出電壓:0.5 V ~ 1.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-QFN（7x7） 包裝:管件 |
| ISL6556ACRZ-TR5208 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL6556BCB | 功能描述:IC CTRLR MULTIPHASE VRM10 28SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,000 系列:- 應(yīng)用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應(yīng)商設(shè)備封裝:42-WLP 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。