參數(shù)資料
型號(hào)： ISL6566A
廠商： Intersil Corporation
英文描述： Three-Phase Buck PWM Controller with Two Integrated MOSFET Drivers and One External Driver Signal
中文描述： 三相降壓PWM控制器，帶有兩個(gè)集成MOSFET驅(qū)動(dòng)器和一個(gè)外部驅(qū)動(dòng)器的信號(hào)
文件頁(yè)數(shù)： 10/28頁(yè)
文件大小： 784K
代理商： ISL6566A
10
FN9200.2
July 27, 2005
V
COMP
voltage crosses the sawtooth ramp, the PWM output
transitions high. The internal or external MOSFET driver
detects the change in state of the PWM signal and turns off
the synchronous MOSFET and turns on the upper MOSFET.
The PWM signal will remain high until the pulse termination
signal marks the beginning of the next cycle by triggering the
PWM signal low.
Channel-Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, I
n
,
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, I
AVG
, provides a measure of the total load-
current demand on the converter during each switching
cycle. Channel-current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current-
balance method is illustrated in Figure 3, with error
correction for channel 1 represented. In the figure, the cycle
average current, I
AVG
, is compared with the channel 1
sample, I
1
, to create an error signal I
ER
.
The filtered error signal modifies the pulse width
commanded by V
COMP
to correct any unbalance and force
I
ER
toward zero. The same method for error signal
correction is applied to each active channel.
Current Sampling
In order to realize proper current-balance, the currents in
each channel must be sampled every switching cycle. This
sampling occurs during the forced off-time, following a PWM
transition low. During this time the current-sense amplifier
uses the ISEN inputs to reproduce a signal proportional to
the inductor current, I
L
. This sensed current, I
SEN
, is simply
a scaled version of the inductor current. The sample window
opens exactly 1/6 of the switching period, t
SW
, after the
PWM transitions low. The sample window then stays open
the rest of the switching cycle until PWM transitions high
again, as illustrated in Figure 4.
The sampled current, at the end of the t
SAMPLE
, is
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used only
for channel-current balance.
The ISL6566A supports MOSFET r
DS(ON)
current sensing
to sample each channel’s current for channel-current
balance. The internal circuitry, shown in Figure 5 represents
channel n of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
active depending on the status of the PVCC3 and PVCC2
pins, as described in the
PWM Operation
section.
FIGURE 3. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
÷
N
I
AVG
I
3
I
2
Σ
-
+
+
-
+
-
f(s)
PWM1
I
1
V
COMP
SAWTOOTH SIGNAL
I
ER
NOTE: Channel 2 and 3 are optional.
FILTER
TO GATE
CONTROL
LOGIC
FIGURE 4. SAMPLE AND HOLD TIMING
TIME
PWM
I
L
I
SEN
SWITCHING PERIOD
SAMPLING PERIOD
OLD SAMPLE
CURRENT
NEW SAMPLE
CURRENT
ISL6566A
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