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參數(shù)資料
| 型號(hào)： | ISL6566A |
| 廠商： | Intersil Corporation |
| 英文描述： | Three-Phase Buck PWM Controller with Two Integrated MOSFET Drivers and One External Driver Signal |
| 中文描述： | 三相降壓PWM控制器，帶有兩個(gè)集成MOSFET驅(qū)動(dòng)器和一個(gè)外部驅(qū)動(dòng)器的信號(hào) |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 784K |
| 代理商： | ISL6566A |
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15
FN9200.2
July 27, 2005
Once the desired output offset voltage has been determined,
use the following formulas to set R
OFS
:
For Positive Offset (connect R
OFS
to GND):
×
OFFSET
For Negative Offset (connect R
OFS
to VCC):
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs. The core-voltage regulator is required to monitor the
DAC inputs and respond to on-the-fly VID changes in a
controlled manner, supervising a safe output voltage transition
without discontinuity or disruption.
The DAC mode the ISL6566A is operating in determines
how the controller responds to a dynamic VID change. When
in VRM10 mode the ISL6566A checks the VID inputs six
times every switching cycle. If a new code is established and
it stays the same for 3 consecutive readings, the ISL6566A
recognizes the change and increments the reference.
Specific to VRM10, the processor controls the VID
transitions and is responsible for incrementing or
decrementing one VID step at a time. In VRM10 setting, the
ISL6566A will immediately change the reference to the new
requested value as soon as the request is validated; in
cases where the reference step is too large, the sudden
change can trigger overcurrent or overvoltage events.
In order to ensure the smooth transition of output voltage
during a VRM10 VID change, a VID step change smoothing
network is required for an ISL6566A based voltage regulator.
This network is composed of a 1k
internal resistor between
the output of DAC and the capacitor C
REF
, between the REF
pin and ground. The selection of C
REF
is based on the time
duration for 1 bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every T
VID
, the relationship between C
REF
and T
VID
is
given by Equation 10.
As an example, for a VID step change rate of 5
μ
s per bit, the
value of C
REF
is 22nF based on Equation 10.
When running in VRM9 or AMD Hammer operation, the
ISL6566A responds slightly different to a dynamic VID change
than when in VRM10 mode. In these modes the VID code can
be changed by more than a 1-bit step at a time. Once the
controller receives the new VID code it waits half of a phase
cycle and then begins slewing the DAC 12.5mV every phase
cycle, until the VID and DAC are equal. Thus, the total time
required for a VID change, t
DVID
, is dependent on the switching
frequency (f
S
), the size of the change (
V
VID
), and the time
required to register the VID change. The one-cycle addition in
the t
DVID
equation is due to the possibility that the VID code
change may occur up to one full switching cycle before being
recognized. The approximate time required for a ISL6566A-
based converter in AMD Hammer configuration running at f
S
=
335kHz to make a 1.1V to 1.5V reference voltage change is
about 100
μ
s, as calculated using the following equation.
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
efficiency from the reduced freewheeling time of the lower
MOSFET body-diode conduction, and to prevent the upper and
lower MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released
to rise. An auto-zero comparator is used to correct the r
DS(ON)
drop in the phase voltage preventing false detection of the
-0.3V phase level during r
DS(ON
conduction period. In the case
of zero current, the UGATE is released after 35ns delay of the
LGATE dropping below 0.5V. During the phase detection, the
disturbance of LGATE falling transition on the PHASE node is
blanked out to prevent falsely tripping. Once the PHASE is
high, the advanced adaptive shoot-through circuitry monitors
E/A
FB
OFS
VCC
GND
+
-
+
-
0.5V
1.5V
VCC
R
OFS
R
FB
VDIFF
ISL6566A
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VREF
V
OFS
+
-
I
OFS
(EQ. 8)
R
OFS
0.5
--------------------------
R
=
(EQ. 9)
R
OFS
1.5
OFFSET
R
×
--------------------------
=
C
REF
0.004X T
VID
=
(EQ. 10)
(EQ. 11)
t
DVID
1
f
S
----
V
-----------------
1.5
+
=
ISL6566A
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