參數(shù)資料
型號: ISL98001CQZ-210
廠商: INTERSIL CORP
元件分類: 消費家電
英文描述: Triple Video Digitizer with Digital PLL
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝: 14 x 20 MM, ROHS COMPLIANT, PLASTIC, MS-022, MQFP-128
文件頁數(shù): 13/29頁
文件大?。?/td> 470K
代理商: ISL98001CQZ-210
13
FN6148.0
October 25, 2005
0x05
Input configuration (0x00)
0
Channel Select
0: VGA1
1: VGA2
1
Input Coupling
0: AC coupled (positive input connected to clamp
DAC during clamp time, negative input disconnected
from outside pad and always internally tied to
appropriate clamp DAC).
1: DC coupled (+ and - inputs are brought to pads and
never connected to clamp DACs). Analog clamp
signal is turned off in this mode.
2
RGB/YPbPr
0: RGB inputs
Base ABLC target code = 0x00 for R, G, and B)
1: YPbPr inputs
Base ABLC target code = 0x00 for G (Y)
Base ABLC target code = 0x80 for R (Pr) and B (Pb)
3
Sync Type
0: Separate HSYNC/VSYNC
1: Composite (from SOG or CSYNC on HSYNC)
4
Composite Sync
Source
0: SOG
IN
1: HSYNC
IN
Note: If Sync Type = 0, the multiplexer will pass
HSYNC
IN
regardless of the state of this bit.
5
COAST CLAMP
enable
0: DC restore clamping and ABLC suspended
during COAST.
1: DC restore clamping and ABLC continue during
COAST.
6
Sync Mask Disable
0: Interval between HSYNC pulses masked
(preventing PLL from seeing Macrovision and any
spurious glitches).
1: Interval between HSYNC pulses not masked
(Macrovision will cause PLL to lose lock).
7
HSYNC
OUT
Mask
Disable
0: HSYNC
OUT
signal is masked (any Macrovision,
sync glitches on incoming SYNC are stripped from
HSYNC
OUT
).
1: HSYNC
OUT
signal is not masked (any
Macrovision, sync glitches on incoming SYNC
appear on HSYNC
OUT
).
If Sync Mask Disable = 1, HSYNC
OUT
is not masked.
0x06
Red Gain (0x55)
7:0
Red Gain
Channel gain, where:
gain (V/V) = 0.5 + [7:0]/170
0x00: gain = 0.5V/V
(1.4V
P-P
input = full range of ADC)
0x55: gain = 1.0V/V
(0.7V
P-P
input = full range of ADC)
0xFF: gain = 2.0V/V
(0.35V
P-P
input = full range of ADC)
0x07
Green Gain (0x55)
7:0
Green Gain
0x08
Blue Gain (0x55)
7:0
Blue Gain
Register Listing
(Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(S)
FUNCTION NAME
DESCRIPTION
ISL98001
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