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參數(shù)資料
| 型號： | ISL98001CQZ-210 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Triple Video Digitizer with Digital PLL |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | 14 x 20 MM, ROHS COMPLIANT, PLASTIC, MS-022, MQFP-128 |
| 文件頁數(shù)： | 21/29頁 |
| 文件大?。?/td> | 470K |
| 代理商： | ISL98001CQZ-210 |
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21
FN6148.0
October 25, 2005
The mask signal is also applied to the HSYNC
OUT
signal.
When Sync Mask Disable = 0, any Macrovision present on
the incoming sync will not be visible on HSYNC
OUT
. If the
application requires the Macrovision pulses to be visible on
HSYNC
OUT
, set the HSYNC
OUT
Mask Disable bit (register
0x05 bit 7).
Headswitching from Analog Videotape Signals
Occasionally this AFE may be used to digitize signals
coming from analog videotape sources. The most common
example of this is a Digital VCR (which for best signal quality
would be connected to this AFE with a component YPbPr
connection). If the digital VCR is playing an older analog
VHS tape, the sync signals from the VCR may contain the
worst of the traditional analog tape artifacts: headswitching.
Headswitching is traditionally the enemy of PLLs with large
capture ranges, because a headswitch can cause the
HSYNC period to change by as much as ±90%. To the PLL,
this can look like a frequency change of -50% to greater than
+900%, causing errors in the output frequency (and
obviously the phase) to change. Subsequent HSYNCs have
the correct, original period, but most analog PLLs will take
dozens of lines to settle back to the correct frequency and
phase after a headswitch disturbance. This causes the top of
the image to “tear” during normal playback. In “trick modes”
(fast forward and rewind), the HSYNC signal has multiple
headswitch-like discontinuities, and many PLLs never settle
to the correct value before the next headswitch, rendering
the image completely unintelligible.
Intersil’s DPLL has the capability to correct large phase
changes almost instantly by maximizing the phase error gain
while keeping the frequency gain relatively low. This is done
by changing the contents of register 0x1C to 0x4C. This
increases the phase error gain to 100%. Because a phase
setting this high will slightly increase jitter, the default setting
(0x49) for register 0x1C is recommended for all other sync
sources.
PGA
The ISL98001’s Programmable Gain Amplifier (PGA) has a
nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB).
The transfer function is:
where GainCode is the value in the Gain register for that
particular color. Note that for a gain of 1V/V, the GainCode
should be 85 (0x55). This is a different center value than the
128 (0x80) value used by some other AFEs, so the firmware
should take this into account when adjusting gains.
The PGAs are updated by the internal clamp signal once per
line. In normal operation this means that there is a maximum
0:
VGA1
0x05[0]
1:
VGA2
HSYNC
IN
1
HSYNC1
SLICER
0x03[2:0]
VSYNC
IN
1
SOG
IN
1
HSYNC2
SLICER
0x03[6:4]
HSYNC
IN
VSYNC
IN
ACTIVITY 0x01[6:0]
&
POLARITY 0x02[5:0]
DETECT
HSYNC
IN
2
VSYNC
IN
2
SOG
IN
2
SYNC
SPLITTER
PLL
0x0E through 0x13
HSYNC
OUT
VSYNC
OUT
COAST
GENERATION
0x11, 0x12, 0x13[2]
XTAL
IN
XTAL
OUT
0: ÷1
0x13
[6]
1: ÷2
÷2
XTALCLOCK
OUT
Output
Formatter
0x18,
0x19,
0x1A
Pixel Data
from AFE
24
R
P
[7:0]
R
S
[7:0]
G
P
[7:0]
G
S
[7:0]
B
P
[7:0]
B
S
[7:0]
DATACLK
HS
OUT
VS
OUT
SOG
IN
SOG
SLICER
0x1C
SOG
SLICER
0x1C
00, 10,
11:
HSYNC
IN
0x05[4:3]
01:
SOG
IN
1:
SYNC
SPLTR
0x05[3]
0:
VSYNC
IN
CLOCKINV
IN
HS
PIXCLK
CSYNC
SOURCE
SYNC
TYPE
VSYNC
DATACLK
FIGURE 8. SYNC FLOW
GainV
0.5
170
GainCode
+
=
ISL98001
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISL98001CQZ-240 | 功能描述:IC TRPL VIDEO DIGITIZER 128-MQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| ISL98001CQZ-275 | 功能描述:IC TRPL VIDEO DIGITIZER 128-MQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| ISL98001CQZ-EVALZ | 功能描述:EVALUATION BOARD ISL98001CQZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| ISL98001CQZ-R5296 | 制造商:Intersil Corporation 功能描述:ISL98001CQZ PB-FREE TRIPLE VIDEO DIGITIZER W/ DIGITAL PLL, T - Trays |
| ISL98001IQZ-140 | 功能描述:IC TRPL VIDEO DIGITIZER 128-MQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標準包裝:250 系列:- 類型:電平移位器 應用:LCD 電視機/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應商設備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
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