參數(shù)資料
型號(hào)： ISL98001CQZ-210
廠商： INTERSIL CORP
元件分類： 消費(fèi)家電
英文描述： Triple Video Digitizer with Digital PLL
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： 14 x 20 MM, ROHS COMPLIANT, PLASTIC, MS-022, MQFP-128
文件頁(yè)數(shù)： 23/29頁(yè)
文件大?。?/td> 470K
代理商： ISL98001CQZ-210
23
FN6148.0
October 25, 2005
Sampling Phase
The ISL98001 provides 64 low-jitter phase choices per pixel
period, allowing the firmware to precisely select the optimum
sampling point. The sampling phase register is 0x10.
HSYNC Slicer
To further minimize jitter, the HSYNC inputs are treated as
analog signals, and brought into a precision slicer block with
thresholds programmable in 400mV steps with 240mV of
hysteresis, and a subsequent digital glitch filter that ignores
any HSYNC transitions within 100ns of the initial transition.
This processing greatly increases the AFE’s rejection of
ringing and reflections on the HSYNC line and allows the
AFE to perform well even with pathological HSYNC signals.
Voltages given above and in the HSYNC Slicer register
description are with respect to a 3.3V sync signal at the
HSYNC
IN
input pin. To achieve 5V compatibility, a 680
series resistor should be placed between the HSYNC source
and the HSYNC
IN
input pin. Relative to a 5V input, the
hysteresis will be 240mV*5V/3.3V = 360mV, and the slicer
step size will be 400mV*5V/3.3V = 600mV per step.
SOG Slicer
The SOG input has programmable threshold, 40mV of
hysteresis, and an optional low pass filter that can be used to
remove high frequency video spikes (generated by overzealous
video peaking in a DVD player, for example) that can cause
false SOG triggers. The SOG threshold sets the comparator
threshold relative to the sync tip (the bottom of the SOG pulse).
SYNC Status and Polarity Detection
The SYNC Status register (0x01) and the SYNC Polarity
register (0x02) continuously monitor all 6 sync inputs
(VSYNC
IN
, HSYNC
IN
, and SOG
IN
for each of 2 channels)
and report their status. However, accurate sync activity
detection is always a challenge. Noise and repetitive video
patterns on the Green channel may look like SOG activity
when there actually is no SOG signal, while non-standard
SOG signals and trilevel sync signals may have amplitudes
below the default SOG slicer levels and not be easily
detected. As a consequence, not all of the activity detect bits
in the ISL98001 are correct under all conditions.
Table 5 shows how to use the SYNC Status register (0x01)
to identify the presence of and type of a sync source. The
firmware should go through the table in the order shown,
stopping at the first entry that matches the activity indicators
in the SYNC Status register.
Final validation of composite sync sources (SOG or
Composite sync on HSYNC) should be done by setting the
Input Configuration register (0x05) to the composite sync
source determined by this table, and confirming that the
CSYNC detect bit is set.
The accuracy of the Trilevel Sync detect bit can be increased
by multiple reads of the Trilevel Sync detect bit. See the
Trilevel Sync Detect
section for more details.
For best SOG operation, the SOG low pass filter (register
0x04[4] should always be enabled to reject the high
frequency peaking often seen on video signals.
HSYNC and VSYNC Activity Detect
Activity on these bits always indicates valid sync pulses, so
they should have the highest priority and be used even if the
SOG activity bit is also set.
SOG Activity Detect
The SOG activity detect bit monitors the output of the SOG
slicer, looking for 64 consecutive pulses with the same period
and duty cycle. If there is no signal on the Green (or Y)
channel, the SOG slicer will clamp the video to a DC level and
will reject any sporadic noise. There should be no false
positive SOG detects if there is no video on Green (or Y).
If there is video on Green (or Y) with no valid SOG signal,
the SOG activity detect bit may sometimes report false
positives (it will detect SOG when no SOG is actually
present). This is due to the presence of video with a
repetitive pattern that creates a waveform similar to SOG.
For example, the desktop of a PC operating system is black
during the front porch, horizontal sync, and back porch, then
increases to a larger value for the video portion of the
screen. This creates a repetitive video waveform very similar
to SOG that may falsely trigger the SOG Activity detect bit.
However, in these cases where there is active video without
SOG, the SYNC information will be provided either as
separate H and V sync on HSYNC
IN
and VSYNC
IN
, or
composite sync on HSYNC
IN
. HSYNC
IN
and VSYNC
IN
should therefore be used to qualify SOG. The SOG Active bit
should only be considered valid if HSYNC Activity
Detect = 0. Note: Some pattern generators can output
HSYNC and SOG simultaneously, in which case both the
HSYNC and the SOG activity bits will be set, and valid. Even
in this case, however, the monitor should still choose
HSYNC over SOG.
TriLevel Sync Detect
Unlike SOG detect, the TriLevel Sync detect function does
not check for 64 consecutive trilevel pulses in a row, and is
therefore less robust than the SOG detect function. It will
report false positives for SOG-less video for the same
reasons the SOG activity detect does, and should therefore
be qualified with both HSYNC and SOG. TriLevel Sync
Detect should only be considered valid if HSYNC Activity
Detect = 0 and SOG Activity Detect = 1.
ISL98001
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