參數(shù)資料
型號(hào)： ISL98001CQZ-240
廠商： INTERSIL CORP
元件分類： 消費(fèi)家電
英文描述： Triple Video Digitizer with Digital PLL
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： 14 x 20 MM, ROHS COMPLIANT, PLASTIC, MS-022, MQFP-128
文件頁(yè)數(shù)： 12/29頁(yè)
文件大?。?/td> 470K
代理商： ISL98001CQZ-240
12
FN6148.0
October 25, 2005
Register Listing
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(S)
FUNCTION NAME
DESCRIPTION
0x00
Device ID
(read only)
3:0
Device Revision
1 = initial silicon, 2 = second revision, etc.
7:4
Device ID
1 = ISL98001
0x01
SYNC Status
(read only)
0
HSYNC1 Active
0: HSYNC1 is Inactive
1: HSYNC1 is Active
1
HSYNC2 Active
0: HSYNC2 is Inactive
1: HSYNC2 is Active
2
VSYNC1 Active
0: VSYNC1 is Inactive
1: VSYNC1 is Active
3
VSYNC2 Active
0: VSYNC2 is Inactive
1: VSYNC2 is Active
4
SOG1 Active
0: SOG1 is Inactive
1: SOG1 is Active
5
SOG2 Active
0: SOG2 is Inactive
1: SOG2 is Active
6
PLL Locked
0: PLL is unlocked
1: PLL is locked to incoming HSYNC
7
CSYNC Detect at
Sync Splitter
0: Composite Sync signal not detected
1: Composite Sync signal is detected
0x02
SYNC Polarity
(read only)
0
HSYNC1
Polarity
0: HSYNC1 is Active High
1: HSYNC1 is Active Low
1
HSYNC2
Polarity
0: HSYNC2 is Active High
1: HSYNC2 is Active Low
2
VSYNC1
Polarity
0: VSYNC1 is Active High
1: VSYNC1 is Active Low
3
VSYNC2
Polarity
0: VSYNC2 is Active High
1: VSYNC2 is Active Low
4
HSYNC1
Trilevel
0: HSYNC1 is Standard Sync
1: HSYNC1 is Trilevel Sync
5
HSYNC2
Trilevel
0: HSYNC2 is Standard Sync
1: HSYNC2 is Trilevel Sync
7:6
N/A
Returns 0
0x03
HSYNC Slicer (0x33)
2:0
HSYNC1 Threshold
000 = lowest (0.4V)
All values referred to
011 = default (1.6V)
voltage at HSYNC input
111 = highest (3.2V)
pin, 240mV hysteresis
3
Reserved
Set to 00
6:4
HSYNC2 Threshold
See HSYNC1
7
Disable Glitch Filter
0: HSYNC/VSYNC Glitch Filter Enabled (default)
1: HSYNC/VSYNC Glitch Filter Disabled
0x04
SOG Slicer (0x16)
3:0
SOG1 and SOG2
Threshold
0x0 = lowest (0mV)
0x6 = default (120mV)
20mV step size
0xF = highest (300mV)
4
SOG Filter
Enable
0: SOG low pass filter disabled
1: SOG low pass filter enabled, 14MHz corner
(default)
5
SOG Hysteresis
Disable
0: 40mV SOG hysteresis enabled
1: 40mV SOG hysteresis disabled (default)
7:6
Reserved
Set to 00.
ISL98001
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