- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383182 > ISL98001CQZ-240 (INTERSIL CORP) Triple Video Digitizer with Digital PLL PDF資料下載
參數(shù)資料
| 型號： | ISL98001CQZ-240 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Triple Video Digitizer with Digital PLL |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | 14 x 20 MM, ROHS COMPLIANT, PLASTIC, MS-022, MQFP-128 |
| 文件頁數(shù)： | 18/29頁 |
| 文件大?。?/td> | 470K |
| 代理商： | ISL98001CQZ-240 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
18
FN6148.0
October 25, 2005
Technical Highlights
The ISL98001 provides all the features of traditional triple
channel video AFEs, but adds several next-generation
enhancements, bringing performance and ease of use to
new levels.
DPLL
All video AFEs must phase lock to an HSYNC signal,
supplied either directly or embedded in the video stream
(Sync On Green). Historically this has been implemented as
a traditional analog PLL. At SXGA and lower resolutions, an
analog PLL solution has proven adequate, if somewhat
troublesome (due to the need to adjust charge pump
currents, VCO ranges and other parameters to find the
optimum trade-off for a wide range of pixel rates).
As display resolutions and refresh rates have increased,
however, the pixel period has shrunk. An XGA pixel at a
60Hz refresh rate has 15.4ns to change and settle to its new
value. But at UXGA 75Hz, the pixel period is 4.9ns. Most
consumer graphics cards (even the ones with “350MHz”
DACs) spend most of that time slewing to the new pixel
value. The pixel may settle to its final value with 1ns or less
before it begins slewing to the next pixel. In many cases it
rings and never settles at all. So precision, low-jitter
sampling is a fundamental requirement at these speeds, and
a difficult one for an analog PLL to meet.
The ISL98001's DPLL has less than 250ps of jitter, peak to
peak, and independent of the pixel rate. The DPLL generates
64 phase steps per pixel (vs. the industry standard 32), for
fine, accurate positioning of the sampling point. The crystal-
locked NCO inside the DPLL completely eliminates drift due to
charge pump leakage, so there is inherently no frequency or
phase change across a line. An intelligent all-digital loop filter/
controller eliminates the need for the user to have to program
or change anything (except for the number of pixels) to lock
over a range from interlaced video (10MHz or higher) to
UXGA 60Hz (170MHz, with the ISL98001-170).
The DPLL eliminates much of the performance limitations and
complexity associated with noise-free digitization of high
speed signals.
Automatic Black Level Compensation (ABLC)
and Gain Control
Traditional video AFEs have an offset DAC prior to the ADC,
to both correct for offsets on the incoming video signals and
add/subtract an offset for user “brightness control” without
sacrificing the 8-bit dynamic range of the ADC. This solution
is adequate, but it places significant requirements on the
system's firmware, which must execute a loop that detects
the black portion of the signal and then servos the offset
DACs until that offset is nulled (or produces the desired ADC
output code). Once this has been accomplished, the offset
(both the offset in the AFE and the offset of the video card
0x25
Sync Separator Control (0x00)
0
Three-state Sync
Outputs
0: VSYNC
OUT
, HSYNC
OUT
, VS
OUT
, HS
OUT
are
active (default).
1: VSYNC
OUT
, HSYNC
OUT
, VS
OUT
, HS
OUT
are in
three-state.
1
COAST Polarity
0: Coast active high (default)
1: Coast active low
Set to 0 for internal VSYNC extracted from CSYNC.
Set to 0 or 1 as appropriate to match external VSYNC
or external COAST.
2
HS
OUT
Lock Edge
0: HS
OUT
's
trailing
edge is locked to selected
HSYNC
IN
's lock edge. Leading edge moves
backward in time as HS
OUT
width is increased
(X980xx default).
1: HS
OUT
's
leading
HSYNC
IN
's lock edge. Trailing edge moves forward
in time as HS
OUT
width is increased.
3
Reserved
Set to 0
4
VSYNC
OUT
Mode
0: VSYNC
OUT
is aligned to HSYNC
OUT
edge,
providing “perfect” VSYNC signal (default).
1: VSYNC
OUT
is “raw” integrator output.
5
Reserved
Set to 0
6
Reserved
Set to 0
7
VS
OUT
Mode
0: VS
OUT
is output on VS
OUT
pin (default).
1: COAST (including pre- and post-coast COAST) is
output on VS
OUT
pin.
Register Listing
(Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(S)
FUNCTION NAME
DESCRIPTION
ISL98001
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL98001CQZ-275 | Triple Video Digitizer with Digital PLL |
| ISL98001 | Triple Video Digitizer with Digital PLL |
| ISL9R1560G2 | 8A, 600V Stealth Diode(8A，600V Stealth二極管) |
| ISO213 | Two-Port Isolated, Low Profile Isolated Instrumentation Amplifier(兩端口隔離、低外形隔離儀用放大器) |
| ISO254 | Precision, Powered, Three-Port Isolated Programmable Gain Amplifier(精密、三端口隔離緩沖放大器(帶變壓器）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL98001CQZ-275 | 功能描述:IC TRPL VIDEO DIGITIZER 128-MQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| ISL98001CQZ-EVALZ | 功能描述:EVALUATION BOARD ISL98001CQZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| ISL98001CQZ-R5296 | 制造商:Intersil Corporation 功能描述:ISL98001CQZ PB-FREE TRIPLE VIDEO DIGITIZER W/ DIGITAL PLL, T - Trays |
| ISL98001IQZ-140 | 功能描述:IC TRPL VIDEO DIGITIZER 128-MQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標準包裝:250 系列:- 類型:電平移位器 應用:LCD 電視機/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| ISL98002CRZ-140 | 功能描述:IC VID DIGITIZER 3CHN AFE 72-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復。