參數(shù)資料
型號(hào): ISP1160
廠商: NXP Semiconductors N.V.
英文描述: Embedded Universal Serial Bus Host Controller
中文描述: 嵌入式通用串行總線主控制器
文件頁數(shù): 60/88頁
文件大小: 2044K
代理商: ISP1160
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 04 — 04 July 2003
60 of 88
9397 750 11371
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
After this register (24H to read) is read, the bits that are active will not be reset, until
logic 1 is written to the bits in this register (A4H to write) to clear it. To clear all the
enabled bits in this register, the HCD must write FFH to this register.
Code (Hex): 24 —
read
Code (Hex): A4 —
write
Table 42:
Bit
Symbol
Reset
Access
Bit
Symbol
Hc
μ
PInterrupt register: bit allocation
15
14
13
12
11
10
9
8
reserved
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
HC
R/W
4
R/W
3
R/W
2
AIIEOT
Interrupt
0
R/W
R/W
1
ATLInt
R/W
0
reserved
ClkReady
Suspended
0
R/W
OPR_Reg
reserved
SOFITLInt
Reset
Access
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 43:
Bit
15 to 7
6
Hc
μ
PInterrupt register: bit description
Symbol
Description
-
reserved
ClkReady
0 —
no event
1 —
clock is ready. After a wake-up is sent, there is a wait for clock
ready. Maximum is 1 ms, and typical is 160
μ
s.
0 —
no event
5
HC
Suspended
1 —
the HC has been suspended and no USB activity is sent from
the microprocessor for each ms. When the microprocessor wants
to suspend the HC, the microprocessor must write to the
HcControl register. And when all downstream devices are
suspended, then the HC stops sending SOF; the HC is suspended
by having the HcControl register written into.
0 —
no event
4
OPR_Reg
1 —
there are interrupts from HC side. Need to read HcControl
and HcInterrupt registers to detect type of interrupt on the HC (if
the HC requires the operational register to be updated).
reserved
3
-
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