參數(shù)資料
型號(hào): ISP1161ABD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 92/134頁
文件大?。?/td> 587K
代理商: ISP1161ABD
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
92 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
[2]
[3]
[4]
[5]
[6]
With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2.
Validating an OUT endpoint buffer causes unpredictable behavior of ISP1161A’s DC.
Clearing an IN endpoint buffer causes unpredictable behavior of ISP1161A’s DC.
Reads a copy of the DcStatus register: executing this command does not clear any status bits or interrupt bits.
When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.
During isochronous transfer in 16-bit mode, because N
1023, the firmware must take care of the upper byte.
13.1 Initialization commands
Initialization commands are used during the enumeration process of the USB
network. These commands are used to configure and enable the embedded
endpoints. They also serve to set the USB assigned address of ISP1161A’s DC and
to perform a device reset.
13.1.1
DcEndpointConfiguration register (R/W: 30H–3FH/20H–2FH)
This command is used to access the DcEndpointConfiguration register (ECR) of the
target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The
register bit allocation is shown in
Table 76
. A bus reset will disable all endpoints.
The allocation of FIFO memory only takes place after
all
16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have fixed configurations, they must be included in the initialization
sequence and be configured with their default values (see
Table 66
). Automatic FIFO
allocation starts when endpoint 14 has been configured.
Remark:
If any change is made to an endpoint configuration which affects the
allocated memory (size, enable/disable), the FIFO memory contents of
all
endpoints
becomes invalid. Therefore, all valid data must be removed from enabled endpoints
before changing the configuration.
Code (Hex): 20 to 2F —
write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F —
read (control OUT, control IN, endpoint 1 to 14)
Transaction —
write/read 1 word
Read Endpoint n Error Code
(n = 1 to 14)
Unlock Device
Write/Read DcScratch register
Read Frame Number
Read Chip ID
Read DcInterrupt register
DcErrorCode register
endpoint 1 to 14
all registers with write access
DcScratch register
DcFrameNumber register
DcChipID register
DcInterrupt register
A2 to AF
read 1 word
[5]
B0
B2/B3
B4
B5
C0
write 1 word
write/read 1 word
read 1 word
read 1 word
read 2 words
Table 75:
Name
DC command and register summary
…continued
Destination
Code (Hex)
Transaction
[1]
Table 76:
Bit
Symbol
Reset
Access
DcEndpointConfiguration register: bit allocation
7
6
FIFOEN
EPDIR
0
0
R/W
R/W
5
4
3
2
1
0
DBLBUF
0
R/W
FFOISO
0
R/W
FFOSZ[3:0]
0
0
0
0
R/W
R/W
R/W
R/W
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