參數(shù)資料
型號: ISP1181
廠商: NXP Semiconductors N.V.
英文描述: Full-speed Universal Serial Bus Interface Device(全速通用串行總線接口器件)
中文描述: 全速通用串行總線接口設(shè)備(全速通用串行總線接口器件)
文件頁數(shù): 53/69頁
文件大小: 1655K
代理商: ISP1181
Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
53 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
19.3 Access cycle timing
[1]
[2]
If the access cycle time is less than specified, the READY signal will be LOW until the internal processing has finished.
Commands Acknowledge Setup, Clear Buffer, Validate Buffer and Write Endpoint Configuration require 180 ns to complete.
Fig 24. ALE timing.
handbook, full pagewidth
MGS790
AD
ALE
DATA
tLH
tAVLL
tLLAX
A0
D0
Table 60: Dynamic characteristics: access cycle timing
Symbol
Parameter
Conditions
8-bit bus
16-bit bus
Min
[1]
Unit
Min
[1]
Max
Max
Write command + write data (see
Figure 25
and
Figure 26
)
T
cy(WC-WD)
cycle time for write command,
then write data
T
cy(WD-WD)
cycle time for write data
T
cy(WD-WC)
cycle time for write data, then
write command
Write command + read data (see
Figure 27
and
Figure 28
)
T
cy(WC-RD)
cycle time for write command,
then read data
T
cy(RD-RD)
cycle time for read data
T
cy(RD-WC)
cycle time for read data, then
write command
100
[2]
-
200
-
ns
90
90
-
-
180
180
-
-
ns
ns
100
[2]
-
200
-
ns
90
90
-
-
180
180
-
-
ns
ns
Fig 25. Write command + write data cycle timing.
handbook, full pagewidth
MGT022
Tcy(WC-WD)
Tcy(WD-WD)
command
DATA
WR
data
data
CS
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