參數(shù)資料
型號: ISP1181BBS,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁數(shù): 18/71頁
文件大?。?/td> 351K
代理商: ISP1181BBS,551
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
24 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Read Control IN Conguration
Endpoint Conguration Register
endpoint 0 IN
31
read 1 byte[2]
Read Endpoint n Conguration
(n = 1 to 14)
Endpoint Conguration Register
endpoint 1 to 14
32 to 3F
read 1 byte[2]
Write/Read Device Address
Address Register
B6/B7
write/read 1 byte[2]
Write/Read Mode Register
Mode Register
B8/B9
write/read 1 byte[2]
Write/Read Hardware Conguration Hardware Conguration Register
BA/BB
write/read 2 bytes
Write/Read Interrupt Enable
Register
Interrupt Enable Register
C2/C3
write/read 4 bytes
Write/Read DMA Conguration
DMA Conguration Register
F0/F1
write/read 2 bytes
Write/Read DMA Counter
DMA Counter Register
F2/F3
write/read 2 bytes
Reset Device
resets all registers
F6
-
Data ow commands
Write Control OUT Buffer
illegal: endpoint is read-only
(00)
-
Write Control IN Buffer
FIFO endpoint 0 IN
01
N
≤ 64 bytes
Write Endpoint n Buffer
(n = 1 to 14)
FIFO endpoint 1 to 14 (IN endpoints
only)
02 to 0F
isochronous: N
≤ 1023 bytes
interrupt/bulk: N
≤ 64 bytes
Read Control OUT Buffer
FIFO endpoint 0 OUT
10
N
≤ 64 bytes
Read Control IN Buffer
illegal: endpoint is write-only
(11)
-
Read Endpoint n Buffer
(n = 1 to 14)
FIFO endpoint 1 to 14
(OUT endpoints only)
12 to 1F
isochronous:
N
≤ 1023 bytes[4]
interrupt/bulk: N
≤ 64 bytes
Stall Control OUT Endpoint
Endpoint 0 OUT
40
-
Stall Control IN Endpoint
Endpoint 0 IN
41
-
Stall Endpoint n
(n = 1 to 14)
Endpoint 1 to 14
42 to 4F
-
Read Control OUT Status
Endpoint Status Register
endpoint 0 OUT
50
read 1 byte[2]
Read Control IN Status
Endpoint Status Register
endpoint 0 IN
51
read 1 byte[2]
Read Endpoint n Status
(n = 1 to 14)
Endpoint Status Register n
endpoint 1 to 14
52 to 5F
read 1 byte[2]
Validate Control OUT Buffer
illegal: IN endpoints only[5]
(60)
-
Validate Control IN Buffer
FIFO endpoint 0 IN[5]
61
Validate Endpoint n Buffer
(n = 1 to 14)
FIFO endpoint 1 to 14 (IN endpoints
only)[5]
62 to 6F
Clear Control OUT Buffer
FIFO endpoint 0 OUT
70
Clear Control IN Buffer
illegal[6]
(71)
-
Clear Endpoint n Buffer
(n = 1 to 14)
FIFO endpoint 1 to 14
(OUT endpoints only)[6]
72 to 7F
Unstall Control OUT Endpoint
Endpoint 0 OUT
80
-
Unstall Control IN Endpoint
Endpoint 0 IN
81
-
Table 13:
Command and register summary…continued
Name
Destination
Code (Hex)
Transaction[1]
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