參數(shù)資料
型號(hào)： ISP1181BBS,551
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝： 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁(yè)數(shù)： 59/71頁(yè)
文件大?。?/td> 351K
代理商： ISP1181BBS,551
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
61 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
22.2 Interfacing ISP1181B with an H8S/2357 microcontroller
This section gives a summary of the ISP1181B interface with a H8S/2357 (or
compatible) microcontroller. Aspects discussed are: interrupt handling, address
mapping, DMA and I/O port usage for suspend and remote wake-up control. A typical
interface circuit is shown in Figure 31.
22.2.1
Interrupt handling
ISP1181B: program the Hardware Conguration register to select an active LOW
level for output INT (INTPOL = 0, see Table 20)
H8S/2357: program the IRQ Sense Control Register (ISCRH and ISCRL) to
specify low-level sensing for the IRQ input.
22.2.2
Address mapping in H8S/2357
The H8S/2357 bus controller partitions its 16 Mbyte address space into eight areas
(0 to 7) of 2 Mbyte each. The bus controller will activate one of the outputs CS0 to
CS7 when external address space for the associated area is accessed.
The ISP1181B can be mapped to any address area, allowing easy interfacing when
the ISP1181B is the only peripheral in that area. If in the example circuit for bus
conguration mode 0 (see Figure 31) the ISP1181B is mapped to address FFFF08H
(in area 7), output CS7 of the H8S/2357 can be directly connected to input CS of the
ISP1181B.
The external bus specications, bus width, number of access states and number of
program wait states can be programmed for each address area. The recommended
settings of H8S/2357 for interfacing the ISP1181B are:
8-bit bus in Bus Width Control Register (ABWCR)
enable wait states in Access State Control Register (ASTCR)
1 program wait state in the Wait Control Register (WCRH and WCRL).
22.2.3
Using DMA
The ISP1181B can be congured for several methods of DMA with the H8S/2357 and
other devices. The interface circuit in Figure 31 shows an example of the ISP1181B
working with the H8S/2357 in single-address DACK-only DMA mode. External
devices are not shown.
For single-address DACK-only mode, rmware must program the following settings:
ISP1181B:
– program the DMA Counter register with the total transfer byte count
– program the Hardware Conguration Register to select active level LOW for
DREQ and DACK
– select the target endpoint and transfer direction
– select DACK-only mode and enable DMA transfer.
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