參數(shù)資料
型號: ISP1181BBS,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁數(shù): 4/71頁
文件大小: 351K
代理商: ISP1181BBS,551
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
11 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.
Modes of operation
The ISP1181B has four bus conguration modes, selected via pins BUS_CONF1 and
BUS_CONF0:
Mode 0
16-bit I/O port shared with 16-bit DMA port
Mode 1
reserved
Mode 2
8-bit I/O port shared with 8-bit DMA port
Mode 3
reserved.
The bus congurations for each of these modes are given in Table 3. Typical interface
circuits for each mode are given in Section 22.1.
9.
Endpoint descriptions
Each USB peripheral is logically composed of several independent endpoints. An
endpoint acts as a terminus of a communication ow between the host and the
peripheral. At design time each endpoint is assigned a unique number (endpoint
identier, see Table 4). The combination of the peripheral address (given by the host
during enumeration), the endpoint number and the transfer direction allows each
endpoint to be uniquely referenced.
The ISP1181B has 16 endpoints: endpoint 0 (control IN and OUT) plus 14
congurable endpoints, which can be individually dened as
interrupt/bulk/isochronous, IN or OUT. Each enabled endpoint has an associated
FIFO, which can be accessed either via the parallel I/O interface or via DMA.
9.1 Endpoint access
Table 4 lists the endpoint access modes and programmability. All endpoints support
I/O mode access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is
selected and enabled via bits EPIDX[3:0] and DMAEN of the DMA Conguration
Register. A detailed description of the DMA operation is given in Section 10.
Table 3:
Bus conguration modes
Mode
BUS_CONF[1:0]
PIO width
DMA width
Description
DMAWD = 0
DMAWD = 1
0
D[15:1], AD0
-
D[15:1], AD0
multiplexed address/data on pin AD0;
bus is shared by 16-bit I/O port and
16-bit DMA port
1
0
1
reserved
2
1
0
D[7:1], AD0
-
multiplexed address/data on pin AD0;
bus is shared by 8-bit I/O port and 8-bit
DMA port
3
1
reserved
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