參數(shù)資料
型號: ISP1181DGG
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: INDUCTOR 4.7NH +-.3NH 0402 SMD
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, TSSOP-48
文件頁數(shù): 19/69頁
文件大小: 1655K
代理商: ISP1181DGG
Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
19 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
4. To meet the ‘suspend’ current requirements for a bus-powered device, the
internal clocks must be switched off by clearing bit CLKRUN in the Hardware
Configuration Register.
5. When the firmware has set and cleared the GOSUSP bit in the Mode Register,
the ISP1181 enters ‘suspend’ state. In powered-off application, the ISP1181
asserts output SUSPEND and switches off the internal clocks after 2 ms.
11.1.1
Powered-on application
In powered-on application (PWROFF = 0 in the Hardware Configuration Register) the
power supply of the CPU and other parts of the circuit is not switched off. The CPU is
normally placed in low-power mode. The SUSPEND output of ISP1181 is normally
HIGH and pulses LOW for 10 ms upon a ‘resume’ condition. This signal can be used
to wake up the CPU. The signal timing is shown in
Figure 6
.
In powered-on application ISP1181 drives its output pins, while the inputs are driven
by the application. Bi-directional pins are placed in three-state and driven HIGH or
LOW by the application. A summary of appropriate pin states is given in
Table 12
.
[1]
‘Externally driven’ refers to logic outside the ISP1181.
Fig 6.
Suspend and resume timing for powered-on application.
handbook, full pagewidth
MGS780
WAKEUP
0.5 ms
10 ms
SUSPEND
Table 12: Pin states in powered-on application
Pin
Type
A0
I/O (three-state)
DATA[15:0]
I/O (three-state)
SUSPEND
O
WAKEUP
I
INT
O (three-state)
RESET
I
CS
I
RD
I
WR
I
XTAL1
I
CLKOUT
O (three-state)
Appropriate state
externally driven
[1]
to logic 0 or logic 1
depends on state of inputs RD and CS
ISP1181 drives logic 1
externally driven to logic 1
ISP1181 drives logic 0 or logic 1
externally driven to logic 1
externally driven to logic 0 or logic 1 (default: logic 1)
externally driven to logic 0 or logic 1 (default: logic 1)
externally driven to logic 1
externally driven to logic 1, if external oscillator is used
ISP1181 drives logic 0
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