參數(shù)資料
型號(hào): ISP1181DGG
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: INDUCTOR 4.7NH +-.3NH 0402 SMD
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, TSSOP-48
文件頁(yè)數(shù): 40/69頁(yè)
文件大小: 1655K
代理商: ISP1181DGG
Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
40 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
Table 49: Interrupt Register: bit allocation
Bit
31
Symbol
reserved
Reset
0
Access
R
Bit
23
Symbol
EP14
Reset
0
Access
R
Bit
15
Symbol
EP6
Reset
0
Access
R
Bit
7
Symbol
BUSTATUS
Reset
0
Access
R
30
29
28
27
26
25
24
reserved
0
R
22
EP13
0
R
14
EP5
0
R
6
reserved
0
R
reserved
0
R
21
EP12
0
R
13
EP4
0
R
5
NOSOF
0
R
reserved
0
R
20
EP11
0
R
12
EP3
0
R
4
SOF
0
R
reserved
0
R
19
EP10
0
R
11
EP2
0
R
3
EOT
0
R
reserved
0
R
18
EP9
0
R
10
EP1
0
R
2
SUSPND
0
R
reserved
0
R
17
EP8
0
R
9
EP0IN
0
R
1
RESUME
0
R
reserved
0
R
16
EP7
0
R
8
EP0OUT
0
R
0
RESET
0
R
Table 50: Interrupt Register: bit description
Bit
Symbol
31 to 24
-
23 to 10
EP14 to EP1
9
EP0IN
8
EP0OUT
7
BUSTATUS
6
-
5
NOSOF
Description
reserved
A logic 1 indicates the interrupt source(s): endpoint 14 to 1
A logic 1 indicates the interrupt source: control IN endpoint
A logic 1 indicates the interrupt source: control OUT endpoint
Monitors the current USB bus status (0 = awake, 1 = suspend).
reserved
A logic 1 indicates that an SOF was lost; interrupt is issued
every 1 ms; after 3 missed SOFs ‘suspend’ state is entered.
A logic 1 indicates that a SOF condition was detected.
A logic 1 indicates that an internal EOT condition was generated
by the DMA Counter reaching zero.
A logic 1 indicates that an ‘a(chǎn)wake’ to ‘suspend’ change of state
was detected on the USB bus.
A logic 1 indicates that a ‘resume’ state was detected.
A logic 1 indicates that a bus reset condition was detected,
4
3
SOF
EOT
2
SUSPND
1
0
RESUME
RESET
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