參數(shù)資料
型號: ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 60/150頁
文件大?。?/td> 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
60 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, the
clock signals are routed to all internal circuits of the DC in the ISP1362.
2. The D_SUSPEND/D_WAKEUP pin goes LOW, and the RESUME bit of the
DcInterrupt register is set. This will generate an interrupt if bit IERESUME of the
DcInterruptEnable register is set.
3. 5 ms after starting the wake-up sequence, the DC in the ISP1362 resumes its
normal functionality (this could be set to 100
μ
s by setting pin TEST0 to HIGH).
4. In case of a remote wake-up, the DC in the ISP1362 drives a K-state on the USB
bus for 10 ms.
5. The application restores itself and other system components to normal operating
mode.
6. After wake-up, the internal registers of the DC in the ISP1362 are read and
write-protected to prevent corruption by inadvertent writing during power-up of
external components. The
fi
rmware must send an Unlock Device command to
the DC in the ISP1362 to restore its full functionality.
14. OTG registers
14.1 OtgControl register (R/W: 62H/E2H)
Code (Hex): 62
read
Code (Hex): E2
write
Table 21:
Command (Hex)
Read
62
67
68
69
6A
6C
OTG Control registers summary
Register
Write
E2
OtgControl
N/A
OtgStatus
E8
OtgInterrupt
E9
OtgInterruptEnable
EA
OtgTimer
EC
OtgAltTimer
Width
References
Functionality
16
16
16
16
32
32
Section 14.1 on page 60
Section 14.2 on page 62
Section 14.3 on page 63
Section 14.4 on page 66
Section 14.5 on page 67
Section 14.6 on page 68
OTG Operation registers
Table 22:
Bit
Symbol
OtgControl register: bit allocation
15
14
13
12
11
10
9
8
reserved
OTG_SE0_
EN
0
R/W
3
SEL_CP_
EXT
A_SRP_
DET_EN
0
R/W
2
DISCHRG_
VBUS
A_SEL_
SRP
0
R/W
1
CHRG_
VBUS
SEL_HC_
DC
1
R/W
0
DRV_
VBUS
Reset
Access
Bit
Symbol
-
-
7
-
-
6
-
-
5
-
-
4
LOC_
PULLDN_
DM
1
R/W
LOC_
PULLDN_
DP
1
R/W
A_RDIS_
LCON_EN
LOC_
CONN
Reset
Access
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
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