參數(shù)資料
型號(hào): ISP1583BS,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁(yè)數(shù): 81/100頁(yè)
文件大?。?/td> 508K
代理商: ISP1583BS,551
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
80 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
(1) The device address consists of signals CS1_N, CS0_N, DA2, DA1 and DA0.
(2) The data bus width depends on the PIO access command used. The Task File register access uses 8 bits (DATA[7:0]), except
for Task File register 1F0 that uses 16 bits (DATA[15:0]). DMA commands 04h and 05h also use a 16-bit data bus.
(3) The device can negate READY/IORDY to extend the PIO cycle with wait states. The host determines whether or not to extend
the current cycle after tsu4, following the assertion of DIOR or DIOW. The following three cases are distinguished:
a) Device keeps READY/IORDY released (high-impedance): no wait state is generated.
b) Device negates READY/IORDY during tsu4, but re-asserts READY/IORDY before tsu4 expires: no wait state is generated.
c) Device negates READY/IORDY during tsu4 and keeps READY/IORDY negated for at least 5 ns after tsu4 expires: a wait state
is generated. The cycle is completed as soon as READY/IORDY is re-asserted. For extended read cycles (DIOR asserted), the
read data on lines DATAn must be valid at td1 before READY/IORDY is asserted.
(4) DIOR and DIOW have a programmable polarity: shown here as active LOW signals.
Fig 31. PIO mode timing
HIGH
(write) DATA[7:0](2)
(read) DATA[7:0](2)
device(1)
address
valid
DIOR, DIOW(4)
READY/IORDY(3a)
READY/IORDY(3b)
READY/IORDY(3c)
004aaa921
Tcy1
tsu1
th1
tw2
th2
tw1
tsu2
tsu3
th3(min)
td2
tsu4
tw3
tsu5
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