參數(shù)資料
型號： ISP1761BE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 114/164頁
文件大?。?/td> 767K
代理商： ISP1761BE,551
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
52 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
Table 52.
Power Down Control register (address 0354h) bit description
Symbol
Description
31 to 16
CLK_OFF_
COUNTER
[15:0]
Clock Off Counter: Determines the wake-up status duration after any
wake-up event before the ISP1761 goes back into suspend mode.
This time-out is applicable only if, during the given interval, the host
controller is not programmed back to normal functionality.
03E8h — The default value. It determines the default wake-up interval
of 10 ms. A value of zero implies that the host controller never wakes
up on any of the events. This may be useful when using the ISP1761
as a peripheral to save power by permanently programming the host
controller in suspend.
FFFFh — The maximum value. It determines a maximum wake-up
time of 500 ms.
The setting of this register is based on the 100 kHz
± 40 % LazyClock
frequency. It is a multiple of 10
s period.
Remark: In 16-bit mode, the default value is 17E8h. A write operation
to these bits with any value xes the clock off counter at 1400h. This
value is equivalent to a xed wake-up time of 50 ms.
15 to 13
-
reserved
12
PORT3_PD
Port 3 Pull-Down: Controls port 3 pull-down resistors.
0 — Port 3 internal pull-down resistors are not connected.
1 — Port 3 internal pull-down resistors are connected.
11
PORT2_PD
Port 2 Pull-Down: Controls port 2 pull-down resistors.
0 — Port 2 internal pull-down resistors are not connected.
1 — Port 2 internal pull-down resistors are connected.
10
VBATDET_
PWR
VBAT Detector Powered: Controls the power to the VBAT detector.
0 — VBAT detector is powered or enabled in suspend.
1 — VBAT detector is not powered or disabled in suspend.
9 to 6
-
reserved; write reset value
5
BIASEN
Bias Circuits Powered: Controls the power to internal bias circuits.
0 — Internal bias circuits are not powered in suspend.
1 — Internal bias circuits are powered in suspend.
4
VREG_ON
VREG Powered: Enables or disables the internal 3.3 V and 1.8 V
regulators when the
ISP1761 is in suspend.
0 — Internal regulators are normally powered in suspend.
1 — Internal regulators switch to low power mode (in suspend mode).
3
OC3_PWR
OC3_N Powered: Controls the powering of the overcurrent detection
circuitry for port 3.
0 — Overcurrent detection is powered on or enabled during suspend.
1 — Overcurrent detection is powered off or disabled during suspend.
This may be useful when connecting a faulty device while the system
is in standby.
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