參數(shù)資料
型號(hào)： ISP1761BE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 148/164頁
文件大小： 767K
代理商： ISP1761BE,551
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
83 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
7to0
SA[7:0]
SW — writes
(0
→ 1)
HW — writes
(1
→ 0)
After
processing
-
Species which
SOF the start split needs to be placed.
For OUT token: When the frame number of bits DW1[7:3] matches the
frame number of the USB bus, these bits are checked for one before
they are sent for the
SOF.
For IN token: Only
SOF0, SOF1, SOF2 or SOF3 can be set to 1.
Nothing can be set for
SOF4 and above.
DW3
63
A
SW — sets
HW — resets
-
Active: Write the same value as that in V.
62
H
HW — writes
-
Halt: The Halt bit is set when any microframe transfer status has a
stalled or halted condition.
61
B
HW — writes
-
Babble: This bit corresponds to bit 1 of Status0 to Status7 for every
microframe transfer status.
60
X
HW — writes
-
Transaction Error: This bit corresponds to bit 0 of Status0 to Status7
for every microframe transfer status.
59
SC
SW — writes
0
HW —
updates
-
Start/Complete:
0 — Start split
1 — Complete split
58
reserved
-
57
DT
HW — writes
SW — writes
-
Data Toggle: For an interrupt transfer, set correct bit to start the PTD.
56 to 55
Cerr[1:0]
HW — writes
SW — writes
-
Error Counter: This eld corresponds to the Cerr[1:0] eld in TD.
00 — The transaction will not retry.
11 — The transaction will retry three times. Hardware will decrement
these values.
54 to 44
reserved
-
43 to 32
NrBytes
Transferred
[11:0]
HW — writes
-
Number of Bytes Transferred: This eld indicates the number of
bytes sent or received for this transaction.
DW2
31 to 24
reserved
-
23 to 8
DataStart
Address[15:0]
SW — writes
-
Data Start Address: This is the start address for data that will be sent
or received on or from the USB bus. This is the internal memory
address and not the CPU address.
7to0
Frame[7:0]
SW — writes
-
Bits 7 to 3 is the polling rate in milliseconds. Polling rate is dened as
2(b 1)
SOF; where b = 4 to 16. When b is 4, executed every
millisecond. See Table 77.
DW1
63 to 57
HubAddress
[6:0]
SW — writes
-
Hub Address: This indicates the hub address.
56 to 50
PortNumber
[6:0]
SW — writes
-
Port Number: This indicates the port number of the hub or embedded
TT.
49 to 48
SE[1:0]
SW — writes
-
This depends on the endpoint type and direction. It is valid only for split
transactions. Table 78 applies to start split and complete split only.
Table 76.
Start and complete split for interrupt: bit description …continued
Bit
Symbol
Access
Value Description
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