Specifications ispLSI 1032E USE ispLSI 1032EA FOR NEW DESIGNS Maximum GRP Delay vs GLB Loads GLB Load 3.0 5.0 1 8 16 32 GRP Delay (ns) 4.0 4" />
參數(shù)資料
型號: ISPLSI 1032E-125LTN
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 4/17頁
文件大?。?/td> 0K
描述: IC PLD ISP 64I/O 7.5NS 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: ispLSI® 1000E
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 32
門數(shù): 6000
輸入/輸出數(shù): 64
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
其它名稱: 220-1592
ISPLSI 1032E-125LTN-ND
ISPLSI1032E-125LTN
12
Specifications ispLSI 1032E
USE
ispLSI
1032EA
FOR
NEW
DESIGNS
Maximum GRP Delay vs GLB Loads
GLB Load
3.0
5.0
1
8
16
32
GRP
Delay
(ns)
4.0
4
2.0
6.0
GRP/GLB/1032E
ispLSI 1032E-70
ispLSI 1032E-90/100
ispLSI 1032E-80
ispLSI 1032E-125
1.0
Power Consumption
Figure 3. Typical Device Power Consumption vs fmax
Power consumption in the ispLSI 1032E device depends
on two primary factors: the speed at which the device is
operating, and the number of product terms used. Figure
3 shows the relationship between power and operating
speed.
0127/1032E
fmax (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25°C
100
200
300
0
20
40
60
80
100
I CC
(mA)
ispLSI 1032E
250
150
350
125
CC
I
can be estimated for the ispLSI 1032E using the following equation:
I
(mA) = 15 + (# of PTs * 0.59) + (# of nets * Max freq * 0.0078)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I
estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of I
is sensitive to operating
conditions and the program in the device, the actual I
should be verified.
CC
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