Specifications ispLSI 1048C 9 Maximum GRP Delay vs GLB Loads ispLSI 1048C-70 4 5 6 4 8 12 16 GLB Loads GRP Delay (ns) ispLSI 1048C-50 7 8 9 10 " />
參數(shù)資料
型號(hào): ISPLSI 1048C-50LQ
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 2/15頁
文件大?。?/td> 0K
描述: IC PLD ISP 96I/O 22NS 128PQFP
標(biāo)準(zhǔn)包裝: 24
系列: ispLSI® 1000
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 24.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 48
門數(shù): 8000
輸入/輸出數(shù): 96
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(28x28)
包裝: 托盤
其它名稱: ISPLSI1048C-50LQ
Specifications ispLSI 1048C
9
Maximum GRP Delay vs GLB Loads
ispLSI 1048C-70
4
5
6
4
8
12
16
GLB Loads
GRP
Delay
(ns)
ispLSI 1048C-50
7
8
9
10
3
0126A-48C-80-isp
1
11
Power Consumption
Power consumption in the ispLSI 1048C device depends
on two primary factors: the speed at which the device is
operating, and the number of Product Terms used. Fig-
Figure 3. Typical Device Power Consumption vs fmax
ure 3 shows the relationship between power and operat-
ing speed.
50
100
150
200
250
0
10
20
30
40
506070
fmax (MHz)
I CC
(mA)
Notes: Configuration of Twelve 16-bit Counters
Typical Current at 5V, 25C
ispLSI 1048C
80
0127A-48C-80-isp
ICC can be estimated for the ispLSI 1048C using the following equation:
ICC = 73 + (# of PTs * 0.23) + (# of nets * Max. freq * 0.010) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB
loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating
conditions and the program in the device, the actual ICC should be verified.
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