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參數(shù)資料
| 型號： | ISPLSI 1048C-50LQ |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD ISP 96I/O 22NS 128PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | ispLSI® 1000 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 24.0ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數(shù)目： | 48 |
| 門數(shù)： | 8000 |
| 輸入/輸出數(shù)： | 96 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI1048C-50LQ |
Specifications ispLSI 1048C
2
The device also has a 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
I/O pin with 3-state control. Additionally, all outputs have
selectable polarity, active high or active low. The signal
voltage levels are TTL-compatible, and the output drivers
can source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock as
shown in figure 1. The outputs of the eight GLBs are
connected to a set of 16 universal I/O cells by the ORP.
Each ispLSI 1048C device contains six Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1048C device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0 on the
ispLSI 1048C device). The logic of this GLB allows the
user to create an internal clock from a combination of
internal signals.
Functional Block Diagram
Figure 1. ispLSI 1048C Functional Block Diagram
Output Routing Pool (ORP)
B0
B1
B2
B3
B4
B5
B6
B7
Output Routing Pool (ORP)
C0
C1
C2
C3
C4
C5
C6
C7
Output Routing Pool (ORP)
F7
F6
F5
F4
F3
F2
F1
F0
Input Bus
Output Routing Pool (ORP)
E7
E6
E5
E4
E3
E2
E1
E0
Input Bus
A0
A1
A2
A3
A4
A5
A6
A7
Output
Routing
Pool
(ORP)
Generic
Logic Blocks
(GLBs)
Megablock
Input
Bus
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Clock
Distribution
Network
D7
D6
D5
D4
D3
D2
D1
D0
Output
Routing
Pool
(ORP)
I/O
94
I/O
95
I/O
93
I/O
92
I/O
91
I/O
90
I/O
89
I/O
88
I/O
87
I/O
86
I/O
85
I/O
84
I/O
83
I/O
82
I/O
81
I/O
80
IN
11
I/O
78
I/O
79
I/O
77
I/O
76
I/O
75
I/O
74
I/O
73
I/O
72
I/O
71
I/O
70
I/O
69
I/O
68
I/O
67
I/O
66
I/O
65
I/O
64
IN
9
IN
10
I/O
17
I/O
16
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
SDO/
IN3
Y
0
Y
1
Y
2
Y
3
I/O
33
I/O
32
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
I/O
44
I/O
45
I/O
46
I/O
47
SCLK/
IN 5
IN
4
IN 7
IN 6
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
MODE/IN 1
I/O 4
I/O 5
ispEN
RESET
Input Bus
lnput
Bus
0139F(2)-48B-isp
IN
8
GOE0
GOE1
IN2
ALL
DEVICES
DISCONTINUED
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ispLSI1048C-50LQ | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ispLSI1048C-50LQI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ispLSI1048C-70LQ | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI1048E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1048E_06 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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