參數(shù)資料
型號(hào): ISPPAC-CLK5304S-01T48C
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 12/56頁(yè)
文件大?。?/td> 0K
描述: IC BUFFER FANOUT ISP UNIV 48TQFP
標(biāo)準(zhǔn)包裝: 250
系列: ispClock™
類(lèi)型: 時(shí)鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 是/無(wú)
頻率 - 最大: 267MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤(pán)
Lattice Semiconductor
ispClock5300S Family Data Sheet
2
General Description
The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution
applications. The ispClock5312S, the rst member of the ispClock5300S family, provides up to 12 single-ended
ultra low skew outputs. Each pair of outputs may be independently congured to support separate I/O standards
(LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output provides indepen-
dent programmable control of termination, slew-rate, and timing skew. All conguration information is stored on-
chip in non-volatile E
2CMOS memory.
The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the
on-chip low jitter high-performance PLL. A set of three programmable 5-bit counters can be used to generate three
frequencies derived from the PLL clock. These counters are programmable in powers of 2 only (1, 2, 4, 8, 16, 32).
The clock output from any of the V-dividers can then be routed to any clock output pin through the output routing
matrix. The output routing matrix, in addition, also enables routing of reference clock inputs directly to any output.
The ispClock5300S device can be congured to operate in four modes: zero delay buffer mode, dual non-zero
delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay
buffer mode.
The core functions of all members of the ispClock5300S family are identical. Table 1 summarizes the
ispClock5300S device family.
Table 1. ispClock5300S Family
Figure 1. ispClock5304S Functional Block Diagram
Device
Number of Programmable
Clock Inputs
Number of Programmable
Single-Ended Outputs
ispClock5320S
1 Differential, 2 Single-Ended
20
ispClock5316S
1 Differential, 2 Single-Ended
16
ispClock5312S
1 Differential, 2 Single-Ended
12
ispClock5308S
1 Differential, 2 Single-Ended
8
ispClock5304S
1 Differential, 2 Single-Ended
4
+
VCO
LOOP
FILTER
PHASE
DETECT
LOCK
DETECT
REFA_REFP
REFSEL
VTT_REFB
1
0
OEX
S
A
P
Y
B
_
L
P
K
C
O
L
JTAG INTERFACE
OEY
TDO
TCK
TMS
TDI
SKEW
CONTROL
OUTPUT
DRIVERS
SKEW
CONTROL
OUTPUT
DRIVERS
OUTPUT
DIVIDERS
OUTPUT ROUTING
MATRIX
RESET
V1
V2
V0
BANK_0A
BANK_0B
BANK_1A
BANK_1B
OUTPUT ENABLE
CONTROLS
5-bit
0
1
FBK
REFB_REFN
VTT_REFA
VTT_FBK
相關(guān)PDF資料
PDF描述
VI-24D-IV CONVERTER MOD DC/DC 85V 150W
VI-24B-IV CONVERTER MOD DC/DC 95V 150W
ISPPAC-CLK5304S-01TN48C IC CLOCK PROGRAM BUFFER 48TQFP
VE-25L-MW-S CONVERTER MOD DC/DC 28V 100W
SY100S839VZG TR IC CLOCK GEN 3.3/5V 20-SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5304S-01T48C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5304S-01T48I 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5304S-01T48I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5304S-01T64C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5304S-01T64I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended