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參數(shù)資料
| 型號： | IXDP610PI |
| 廠商： | IXYS |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PWM CTRL BUS DIGITAL 18-PDIP |
| 標準包裝： | 21 |
| 應用： | PWM 電機控制器 |
| 接口： | 微處理器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 封裝/外殼： | 18-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 18-DIP |
| 包裝： | 管件 |
| 安裝類型： | 通孔 |
2001 IXYS/DEI All rights reserved
4
IXDP 610
Description
Introduction
The IXDP610 is a digital PWM con-
troller. It simplifies the interface
between a microprocessor and a
switching power bridge by providing to
a micro-processor the means to directly
control the average voltage across a
load (DC motor, etc.). Since the
IXDP610 generates two
complementary PWM control signals,
there is no need for Digital to Analog
Converters (DACs), Sawtooth
Generators, and Analog Comparators.
OUT1 and OUT2 can directly drive the
buffers to the power transistors.
Use of the IXDP610 in a DC servo
system is depicted in the system block
diagram shown in Fig. 1. The IXDP610
receives digital data from the micropro-
cessor and converts the data to a pair
of complementary PWM signals that
can be used to control the average
voltage across a DC servo motor. A
Shaft Encoder Peripheral Interface
(SEPI) IC converts incremental
encoder signals to a binary number so
the micro-processor can monitor and
complete the control of the DC servo
motor.
It is possible to generate PWM control
signals in software with a dedicated
microprocessor or microcontroller. This
has the limitation, however, of very low
switching frequencies (<5 kHz) and
significant software overhead. By using
the IXDP610 to handle the generation
of the PWM control signals, a micro-
processor can handle several PWM
channels and the PWM control signals
can switch at relatively high rates (up to
300 kHz). Servicing the IXDP610 is a
simple as writing an 8-bit number to the
Pulse Width latch whenever a change
in duty cycle is desired. This is analo-
gous to writing data to a DAC.
Programmable dead-time
Because the IXDP610 is a digital IC,
and is programmable, it is possible to
tailor the dead-time period (defined as
t
DT in Fig. 2). IXDP610’s programmable
dead-time feature is difficult to
duplicate in the equivalent analog
system. The control of a switching
bridge usually involves a process of
alternating the “on-time” of two power
switches connected in series between
a high-voltage and a low-voltage. For
example, the H-bridge of Fig. 3 can be
operated by turning the upper left and
lower right transistors on and leaving
the two remaining transistors off, during
the first half of the PWM cycle. In the
second half of the cycle, the upper right
and lower left transistors are on and
Fig. 1 Basic System Configuration
Fig. 3 IXDP610 to DC Servo Motor Full Bridge Block
Diagram
guaranteeing that both transistors in a
leg are off for a minimum of time during
a transition (the dead-time period).
Since the dead-time is programmable,
it can be tailored to the specific
application. It can be short for high-
speed MOSFETs and longer for IGBTs.
Protection circuitry
The IXDP610 has several features that
facilitate protection of the power devi-
ces being controlled. The ODIS pin is
an input that can be driven by external
hardware under emergency shutdown
conditions, such as over-current and
over-temperature. The Stop bit, in the
Control latch, provides a mechanism
through which the software can indefi-
nitely disable the complementary out-
puts. ODIS and Stop perform similar
functions, they provide a means to
protect the power devices from measu-
rable system hazards such as over-
current, over-voltage, over-temperature
etc.
Software runaway is a system hazard
that is difficult or impossible to
measure. The Lock bit, in the Control
latch, can be used to protect the
system from software runaway and/or
errors. Setting the Lock bit prevents
subsequent writes to the Control latch
from having any affect on the
IXDP610’s operating para-meters.
Setting the Lock bit does not prevent
one from asserting the Stop bit. Once
the Lock bit is set, it is impossible to
modify critical parameters, such as the
dead-time delay or the PWM wave-
form resolution.
Control latch
The Control latch is composed of eight
bits that determine the IXDP610’s
Fig. 2 PWM Cycle Time and Dead-
Time Definition
the remaining two are off. During the
transition, between the first half and the
second half of the PWM cycle, there is
a very short period of time when both
the upper transistor and the lower
transistor in a leg could be on. If both
transistors are on, for this short period
of time, they will effectively short the
high voltage supply to ground-this is an
undesirable situation.
The IXDP610’s programmable dead-
time feature prevents this situation by
SEPI
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相關代理商/技術參數(shù) |
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