參數(shù)資料
型號： IXDP610PI
廠商： IXYS
文件頁數(shù)： 6/8頁
文件大?。?/td> 0K
描述： IC PWM CTRL BUS DIGITAL 18-PDIP
標(biāo)準(zhǔn)包裝： 21
應(yīng)用： PWM 電機(jī)控制器
接口： 微處理器
電源電壓： 4.5 V ~ 5.5 V
封裝/外殼： 18-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 18-DIP
包裝： 管件
安裝類型： 通孔
2001 IXYS/DEI All rights reserved
6
IXDP 610
The Resolution bit in the Control latch
determines whether the number in the
PW latch has 7 significant bits or 8
significant bits. The following formulae
can be used to determine the resulting
PWM waveform’s duty cycle:
For 7-bit mode operation:
PW number
% duty cycle =
x 100
128
For 8-bit mode operation:
PW number
% duty cycle =
x 100
256
The formulae are valid for all PW
num-bers except those at the
Fig. 5 8088 to IXDP610 Interface
PW Number
Resulting
(binary)
Duty
7-Bit
8-Bit
Cycle
Resolution
Resolution %
0000 0000
0000 0000 0.0
0000 0001
0000 0001 0.0
--
0000 0010 0.78125
--
0000 0011 1.171875
0000 0010
0000 0100 1.5625
--
0000 0101 1.953125
0000 0011
0000 0110 2.34375
--
0000 0111 2.734375
0000 0100
0000 1000 3.125
::
:
::
:
::
:
0100 0000
1000 0000 50.0
::
:
::
:
::
:
0111
1101
1111 1010 97.65625
--
1111 1011 98.046875
0111
1110
1111 1100 98.4375
--
1111 1101 98.828125
--
1111 1110 99.21875
0111
1111
1111 1111 100.0
1XXX XXXX
--
100.0
Table 3: Duty Cycle as a Function of PW
Number
extremes. The following table
illustrates the resulting percent duty
cycle for seve-ral PW numbers. (The
complete table would have 256
entries, those entries that have been
omitted can be calcu-lated using the
above formulare.)
The PWM duty cycle byte can be
written to at any time. If the outputs
are disabled by either the Stop bit in
the Control latch or the OUTPUT
DISABLE input, writing to the PWM
duty cycle byte will have no effect on
the outputs. When the outputs are re-
enabled, the duty cycle will be deter-
mined by the last byte written to the
PWM duty cycle byte.
Application Information
Introduction
The IXDP610 is a digital PWM con-
troller intended for use with general-
purpose microprocessors and micro-
controllers. Therefore, it is important
to understand how the microproces-
sor hardware and software interacts
with and affects the operation of the
IXDP610. On the following pages one
will find discussions of some of the
most important hardware and soft-
ware interface issues. Among these
issues are the hardware interface,
how to choose the IXDP610's clock,
initialization of the DPWM, the effect
of the dead-time on the duty cycle,
and the response of the IXDP610 to
changes in the Pulse Width latch
number. The following pages should
be studied carefully by both the
hardware and the software designer.
The IXDP610 can be interfaced with
virtually any microprocessor or micro-
controller. Some interface examples
are shown below.
8051 to IXDP610 Interface
Fig. 4 is an example of how the
IXDP610 can be interfaced with an
Intel 8051 microcontroller. The
interface is very simple and is ideally
suited for servo motor control appli-
cations. The 11.059 MHz clock allows
one to use the 8051's built-in serial
communication hardware at any
standard baud rate. At this clock
frequency, the IXDP610 can be
configured for a 21.6 kHz switching
frequency and a dead-time between
zero and 1.26
s, which is adjustable
in 180 ns steps.
8088 to IXDP610 Interface
Fig. 5 is just one example of how the
IXDP610 can be interfaced with the
Intel 8088 microprocessor. Using a
5 MHz clock (15 MHz crystal) the
IXDP610 can be configured for a
19.53 kHz switching frequency. The
deadtime can be adjusted between 0
and 2.8
s, in 400 ns steps. This confi-
guration is ideally suited for driving DC
servo motor amplifiers that use
MOSFET, IGBT, or bipolar transistors.
Frequency and dead-time
considerations
Typical applications for the IXDP610
include full and half bridge systems.
Shown in Fig. 3 is a full bridge system.
The programmable dead-time feature
of the IXDP610 aids in preventing
shorts in the power bridge and allows
use of either fast MOSFETs or slower
IGBTs and bipolar transistors. Table 4
shows some of the PWM frequency
and dead-time combinations that can
be obtained with the IXDP610. The
various options shown in the table are
selected by varying the CLK frequency
and the Divide and 7/8 bit in the
Fig. 4 8051 to IXDP610 Interface
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