![](http://datasheet.mmic.net.cn/370000/IXHQ100_datasheet_16701600/IXHQ100_7.png)
7
the external load, V
, is zero. As V
rises,
its rate of increase determined by the value of
the external capacitor, C8 (figure1), and the
value of the internal current source, I5. V
's
rate of increase follows V
As soon as V
exceeds V
(figure 1) of the external power
MOSFET, drain current I
starts to flow. The
rate of increase of I
dQ1
is proportional to the rate
of increase of V
, and is independent of the
size of C5 , the total filter capacitance of the
load. Note that this rate, which is directly
proportional to C7 and inversely proportional to
C8, could be adjusted . Similarly the Toff-delay
can be adjusted and is directly proportional to
the size of C7.
Normal Operation
DEVICE OPERTION*
A hot swap operation involves removal and
reinsertion of a device while the system using
it remains in operation. Such an operation
could cause external capacitors to draw cur-
rents high enough to disturb system operations
or even cause permanent damage to both the
device and the system.
The IXHQ100 is designed to prevent any distur-
bances or damage during such occurrences,
allowing the circuit board to be safely inserted
and removed from a live backplane. Capable of
operating under three modes, the chip also acts
as a power active noise filter and an auto-detect
circuit.
Insertion Process
As the circuit board is inserted into the
backplane, physical connections should be
made to ground to discharge any electrostatic
voltage. The insertion process begins when
power and ground are supplied to the board
through pins on the blackplane.
Once power is applied, the IXHQ100 starts up
but does not immediately apply power to the
output load. The internal Power Up Reset logic
(see in Figure 2) turns on for 10
μ
s prior to any
other logic. This pulse goes through two NOR
gates and resets SRFF1 Flip Flop. Once SRFF1
is reset, the current source, I6, charges the
OFFTM pin at a rate proportional to the size of
the external capacitor, C7 (fig 1). During the time
the OFFTM pin is ramping from 0V to Vrf (~5V),
which is the T
V
stays at 0V. After T
greater than Vrf, and COMP1 goes low, driving
N3 to off state. I5 now starts to charge C1,
ramping +ve i/p of OA4. OA4 buffers V
SLOPE
and
sets the GATE output ramp.
,
COMP1 keeps N3 ON so
,
V
ecomes
It is assumed that when the circuit board is first
inserted into the backplane, the voltage across
IXHQ 100PI
IXHQ 100SI
Flip-flop setting and resetting
*Unless otherwise stated, all symbol and device references are referred to the logic diagram (Fig 2) on page 6
The flip-flop, SRFF1 (fig 2), used in the IXHQ100,
is reset dominant. Hence when both S and R
inputs are driven high, the SRFF1 remains
reset. Under normal operation, S input becomes
high whenever OR1 output is high and R input
is low. In turn, OR1 goes high if any one of the
outputs of EXOR1, or COMP2, or COMP3
goes high.
EXOR1 output goes high if it detects the loss of
either Gnd or -Vin. If INV input is connected to
With continuous
–
V
in
applied, the IXHQ100
acts as an active power filter by modulating the
voltage drop across the external Power
MOSFET V
ds
so that any noise on
–
V
in
is
cancelled by V
ds
.
The direct connection of IXHQ 100
’
s AGND pin
to
–
V
in
allows the V
drop
(internally set to ~750mV)
to set the ~90% of the maximum peak noise
voltage reject by the IXHQ100. The internal
V
drop
setting of ~750 mV allows 1.35 Vpp of
noise rejection. Graph on page 5 illustrates the
level of ripple attenuation during normal
conditions. Notice that the noise rejection is very
high (~60db) between 400Hz to 40KHz, which is
optimal for most hot swap applications.