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參數(shù)資料
| 型號： | K4C89093AF-AIF6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 288Mb x18 Network-DRAM2 Specification |
| 中文描述： | 288Mb x18網(wǎng)絡DRAM2規(guī)范 |
| 文件頁數(shù)： | 13/55頁 |
| 文件大?。?/td> | 1470K |
| 代理商： | K4C89093AF-AIF6 |
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K4C89183AF
- 13 -
REV. 0.7 Jan. 2005
AC Test Conditions
Symbol
V
IH
(min)
V
IL
(max)
V
REF
V
TT
V
SWING
V
R
V
ID
(AC)
SLEW
Parameter
Value
V
REF
+ 0.2
V
REF
- 0.2
Units
Notes
Input high voltage (minimum)
V
Input low voltage (maximum)
V
Input reference voltage
VddQ/2
V
Termination voltage
V
REF
V
Input signal peak to peak swing
0.7
V
Differential clock input reference level
V
X(AC)
V
Input differential voltage
1.0
V
Input signal minimum slew rate
2.5
V/ns
V
OTR
Output timing measurement reference voltage
VddQ/2
V
9
V
IH
min
(AC)
V
REF
V
IL
max
(AC)
V
SWING
VddQ
Vss
V
TT
Output
Slew=(V
IH
min
(AC)
- V
IL
max
(AC)
)/
T
T
T
Notes :
1. Transition times are measured between V
IH
min
(DC)
and V
IL
max
(DC)
.
Transition (rise and fall) of input signals have a fixed slope.
2. If the result of nominal calculation with regard to t
CK
contains more than
one decimal place, the result is rounded up to the nearest decimal place.
(i.e., t
DQSS
= 0.8*t
CK
, t
CK
= 3.3ns, 0.8*3.3 ns = 2.64 ns is rounded up to 2.7 ns.)
3. These parameters are measured from the differential clock (CLK and CLK) AC cross point.
4. These parameters are measured from signal transition point of DS crossing V
REF
level.
5. The t
REFI
(MAX.) applies to equally distributed refresh method.
The t
REFI
(MIN.) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In
other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the
maximum.
6. Low Impedance State is speified at VddQ/2± 0.2V from steady state.
7. High Impedance State is specified where output buffer is no longer driven.
8. These parameters depend on the clock jitter. These parameters are measured at stable clock.
9. Output timing is measured by using Normal driver strength at V
DDQ
= 1.7V ~ 1.9V.
Output timing is measured by using Strong driver strength at V
DDQ
= 1.4V ~ 1.6V
AC Test Load
25
Measurement Point
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