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參數(shù)資料
| 型號： | K4D551638D-TC45 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CABLE ASSEMBLY; 2.9mm MALE TO 2.9mm MALE; 40 GHz CABLE |
| 中文描述： | 片256Mbit GDDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 230K |
| 代理商： | K4D551638D-TC45 |
256M GDDR SDRAM
K4D551638D-TC
- 15 -
Rev 1.8 (Oct. 2003)
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming
the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4D551638D-TC50 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
| K4D551638D-TC60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
| K4D551638F-LC40000 | 制造商:Samsung 功能描述:DDR SGRAM X16 TSOP2 - Trays 制造商:Samsung Semiconductor 功能描述:DRAM Chip GDDR SDRAM 256M-Bit 16Mx16 2.6V 66-Pin TSOP-II |
| K4D551638F-TC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
| K4D551638F-TC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
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