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參數(shù)資料
| 型號(hào)： | K4D551638D-TC45 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CABLE ASSEMBLY; 2.9mm MALE TO 2.9mm MALE; 40 GHz CABLE |
| 中文描述： | 片256Mbit GDDR SDRAM內(nèi)存 |
| 文件頁(yè)數(shù)： | 8/18頁(yè) |
| 文件大?。?/td> | 230K |
| 代理商： | K4D551638D-TC45 |
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256M GDDR SDRAM
K4D551638D-TC
- 8 -
Rev 1.8 (Oct. 2003)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A
0
~ A
12
and BA
0
, BA
1
in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A
0
~ A
2
,
addressing mode uses A
3
, CAS latency(read latency from column address) uses A
4
~ A
6
. A
7
is used for test mode. A
8
is
used for DLL reset. A
7,
A
8
, BA
0
and BA
1
must be set to low for normal MRS operation. Refer to the table for specific codes
MODE REGISTER SET(MRS)
Mode Register
CAS Latency
A
6
0
0
0
0
1
1
1
1
A
5
0
0
1
1
0
0
1
1
A
4
0
1
0
1
0
1
0
1
Latency
Reserved
Reserved
Reserved
3
4
Reserved
Reserved
Reserved
Burst Length
A
2
A
1
A
0
Burst Type
Sequential
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
Interleave
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Burst Type
A
3
0
1
Type
Sequential
Interleave
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
MRS Cycle
Command
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum
t
RP
is required to issue MRS command.
CK, CK
Precharge
All Banks
NOP
NOP
MRS
NOP
NOP
2
0
1
5
3
4
8
6
7
Any
NOP
Command
t
RP
t
MRD
=2 t
CK
BA
1
BA
0
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
BA
0
0
1
A
n
~ A
0
MRS
EMRS
DLL
A
8
0
1
DLL Reset
No
Yes
Test Mode
A
7
0
1
mode
Normal
Test
NOP
Address Bus
RFU
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| K4D551638D-TC50 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
| K4D551638D-TC60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
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| K4D551638F-TC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
| K4D551638F-TC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
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