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參數(shù)資料
| 型號： | K4D623238B-GC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Mbit DDR SDRAM |
| 中文描述： | 64Mb的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大小： | 147K |
| 代理商： | K4D623238B-GC |
64M DDR SDRAM
K4D623238B-GC
- 3 -
Rev. 1.4 (Sep. 2002)
The K4D623238 is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 2 x1,048,976 words by 32
bits, fabricated with SAMSUNG
’
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 2.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
2.5V + 5% power supply for device operation
VDD/VDDQ = 2.8V ± 5% for -33
VDD/VDDQ = 2.5V ± 5% for -60/-55/-50/-45/-40
SSTL_2 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 3,4,5 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
Full page burst length for sequential burst type only
Start address of the full page burst should be even
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
No Wrtie-Interrupted by Read Function
GENERAL DESCRIPTION
FEATURES
4 DQS’ s ( 1DQS / Byte )
Data I/O transactions on both edges of Data strobe
DLL aligns DQ and DQS transitions with Clock transition
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
16ms refresh period (2K cycle)
144-Ball FBGA
Maximum clock frequency up to 300MHz
Maximum data rate up to 600Mbps/pin
FOR 512K x 32Bit x 4 Bank DDR SDRAM
512K x 32Bit x 4 Banks Double Data Rate Synchronous RAM
with Bi-directional Data Strobe and DLL
ORDERING INFORMATION
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4D623238B-GC/L33
300MHz
600Mbps/pin
SSTL_2
144-Ball FBGA
K4D623238B-GC/L40
250MHz
500Mbps/pin
K4D623238B-GC/L45
222MHz
444Mbps/pin
K4D623238B-GC/L50
200MHz
400Mbps/pin
K4D623238B-GC/L55
183MHz
366Mbps/pin
K4D623238B-GC/L60
166MHz
333Mbps/pin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4D64163HF | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC33 | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC36 | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC40 | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC50 | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4D623238B-GC/L33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mbit DDR SDRAM |
| K4D623238B-GC/L40 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mbit DDR SDRAM |
| K4D623238B-GC/L45 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mbit DDR SDRAM |
| K4D623238B-GC/L50 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mbit DDR SDRAM |
| K4D623238B-GC/L55 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mbit DDR SDRAM |
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