參數(shù)資料
型號(hào)： K4F640412C-JC450
元件分類： DRAM
英文描述： 16M X 4 FAST PAGE DRAM, 45 ns, PDSO32
封裝： 0.400 INCH, PLASTIC, SOJ-32
文件頁(yè)數(shù)： 19/20頁(yè)
文件大?。?/td> 367K
代理商： K4F640412C-JC450
CMOS DRAM
K4F660412C,K4F640412C
NOTES
An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is
achieved.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1 TTL load and 100pF.
Operation within the
tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If
tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that
tRCD
≥tRCD(max).
tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh
or Vol.
tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric charac-
teristics only. If
tWCS
≥tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
tCWD
≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either
tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge in read-modify-write
cycles.
Operation within the
tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
These specifications are applied in the test mode.
In test mode read cycle, the value of
tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
If
tRASS
≥100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only-Refresh and Burst CAS-before-RAS refresh, 4096 cycles(4K/8K) of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before
and after self refresh in order to meet refresh specification.
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