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參數(shù)資料
| 型號： | K4H560838F-UCC4 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mb F-die DDR400 SDRAM Specification |
| 中文描述： | 256Mb的的F -模具支持DDR400內(nèi)存規(guī)格 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 171K |
| 代理商： | K4H560838F-UCC4 |
DDR SDRAM
DDR SDRAM 256Mb F-die (x8, x16)
Rev. 1.1 August. 2003
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle.
Iout = 0mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N N R0 N N N N P0 N N
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
IDD7A : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing.
Iout = 1mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4H560838F-UCCC | 制造商:Samsung Electro-Mechanics 功能描述:32M X 8 DDR DRAM, 0.65 ns, 66 Pin Plastic SMT |
| K4H560838H | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Product Guide |
| K4H560838H-UC/LA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb H-die DDR SDRAM Specification |
| K4H560838H-UC/LB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb H-die DDR SDRAM Specification |
| K4H560838H-UC/LB3 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb H-die DDR SDRAM Specification |
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